触发器在其时钟非边沿条件之前不保持值

Question

我试图创建一个具有复位启用和同步数据加载的触发器。它在 VHDL 仿真中工作正常，但是当我尝试在 ISE 中综合它时，它给了我以下错误：

Line 24: statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition

代码如下：

library ieee;  
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity D_FF is
port (D: in std_logic;
      clk: in std_logic;
      reset_enable: in std_logic;
      reset: in std_logic;
      Q: out std_logic:='0'
); 
end D_FF;    

architecture a1 of D_FF is
begin
  proc: process (D,clk,reset,reset_enable)
  begin
    if (reset_enable='1') then 
      if (reset='1') then
        q<='0';
      end if;
    end if;
    if (clk'event and clk='1') then -- Line 24
      q<=d; 
    end if; 
  end process proc;
end a1;

如何修复此错误以使代码可综合并与我编写的代码等效？

Answer 1

为您指明正确的方向：当同时存在复位和时钟沿时会发生什么情况？

解决方案：

if (reset = '1' and reset_enable = '1') then
    q <= '0';
elsif (clk'event and clk = '1') then
    q <= d;
end if;

触发器在其时钟非边沿条件之前不保持值

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触发器在其时钟非边沿条件之前不保持值