VHDL-递增和递减按钮

Question

我正在尝试使用两个按钮来递增和递减。该算法运行良好，但我有一个小问题。据说我正在递增，当我尝试递减累加器时，它会再次递增，然后才开始减少。如果我先尝试递减，则相同。如果有人帮助我，我将非常感激。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_unsigned.all;

entity my_offset_controller is
port(clk            : in std_logic;
     input          : in std_logic_vector(15 downto 0);  
     add_button     : in std_logic;  
     sub_button     : in std_logic; 
     output_res     : out std_logic_vector(15 downto 0)
  );  
end my_offset_controller;

architecture Behavioral of my_offset_controller is

signal buttonState_up        : std_logic:='0';
signal accumulator           : std_logic_vector(15 downto 0);
signal lastButtonState_up    : std_logic:='0';
signal buttonState_down      : std_logic:='0';
signal lastButtonState_down  : std_logic:='0';
signal buttonPushCounter     : integer range 0 to 512 :=0;
process(clk)
      begin
        if rising_edge(clk) then 
              buttonState_up   <= add_button;
              buttonState_down <= sub_button;
                   if (buttonState_up /= lastButtonState_up) then 
                              if (buttonState_up ='1')       then 
                                    buttonPushCounter  <=  buttonPushCounter + 1;
                                    accumulator        <=   std_logic_vector(to_unsigned(buttonPushCounter,accumulator'length)); 
                               end if;
                      lastButtonState_up <= buttonState_up;      
                    elsif (buttonState_down /= lastButtonState_down) then 
                              if (buttonState_down ='1')       then 
                                   buttonPushCounter   <=  buttonPushCounter - 1;
                                accumulator        <=  std_logic_vector(to_unsigned(buttonPushCounter,accumulator'length)); 

                               end if;
                     lastButtonState_down <= buttonState_down;
                            end if;
                     end if;
     end process; 

output_res<= accumulator + input ;

我用这个模块来控制我在 vga 屏幕上绘制的信号的偏移量。

Answer 1

没有更多信息很难帮到你。您应该提供一个带有时序图的测试台，以使其更容易。然而，通过查看您的过程，我会说问题来自以下几行：

buttonPushCounter  <=  buttonPushCounter + 1;
accumulator        <=  std_logic_vector(to_unsigned(buttonPushCounter,accumulator'length));

您所做的是在更新 accumulator 的同时增加 buttonPushCounter。这样 buttonPushCounter 将始终根据最后一个事件移动 +1 或 -1。

我可以推荐的是在每个时钟周期而不是每次事件发生时更新 accumulator。例如像这样：

 if rising_edge(clk) then 
    accumulator <= std_logic_vector(to_unsigned(buttonPushCounter,accumulator'length));
    ...

VHDL-递增和递减按钮

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