VHDL Array Initialization Error: "Syntax error near ":="

Question

我有一个数组初始化的书面代码。但它显示我遵循错误。

ERROR:HDLCompiler:806 - "Syntax error near ":=".

ERROR:HDLCompiler:854 - Unit ignored due to previous errors.

library IEEE;
use IEEE.std_logic_1164.all;

entity kelvin is
end kelvin;

architecture ospl of kelvin is
type array_new is array (0 to 1) of integer;

begin
array_new := ('127','126');
    
end ospl;

Answer 1

您所做的是声明一个名为 array_new 的数组类型，您直接为其赋值。您错过了中间的一个步骤，即声明数组类型的对象。

代码行后

type array_new is array (0 to 1) of integer;

您应该声明类型为 array_new 的信号。例如修改后的代码如下所示：

library IEEE;
use IEEE.std_logic_1164.all;

entity kelvin is
end kelvin;

architecture ospl of kelvin is
type array_new is array (0 to 1) of integer;
signal array_new_signal: array_new;

begin
array_new_signal <= (127,126);

end ospl;

Refer this link for further explanation:

VHDL Array Initialization Error: "Syntax error near ":="

VHDL Array Initialization Error: "Syntax error near ":="

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