SystemVerilog 并行约束

SystemVerilog Parallel Constraint

在下面的代码中,位 'a' 在 1 和 0 之间平均分配。另外,它使用并行约束被约束为 1。我最初的猜测是,我们会得到五个 1 和五个失败的随机化。取而代之的是,我们得到了 10 个 1。谁能解释一下背后的原因?

program test1;

    class test;

        rand bit a;

        constraint con1 {a dist {0:=5,1:=5};}

        constraint con2 {a == 1'b1;}

        function display();
            $display(a);
        endfunction

    endclass

    test t;

    initial begin

        t = new();
        repeat(10)
            begin
                assert(t.randomize);
                t.display();
            end

    end

endprogram

1800-2012 LRM 第 18.5.4 节

Absent any other constraints, the probability that the expression matches any value in the list is proportional to its specified weight. If there are constraints on some expressions that cause the distribution weights on these expressions to be not satisfiable, implementations are only required to satisfy the constraints. An exception to this rule is a weight of zero, which is treated as a constraint.

所以和你写的一样

constraint con1 {a dist {1:=5};}