VHDL 中的程序 returns 未知

Question

我必须比较功能代码和 rtl 代码。以下代码是作为 16 位输入的双分量的结构代码编写的。我尝试编写以下电路：

这里附上代码和测试平台：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity two_s_complement_16bit_rtl is
    Port ( A : in  STD_LOGIC_VECTOR (15 downto 0);
           Cout : out  STD_LOGIC_VECTOR (15 downto 0):= (others => '0'));
end two_s_complement_16bit_rtl;

architecture Behavioral of two_s_complement_16bit_rtl is

procedure two_s_complement  (
        A    : in std_logic;
        B    : in std_logic;
        C    : out std_logic;
        cout : out std_logic;
        cin  : in std_logic) is

        begin  

        cout := ((not A) and B) xor (((not A) xor B) and cin);

end procedure;

begin

    process (A)
        variable temp_C, temp_Cout: STD_LOGIC_VECTOR(15 downto 0);
        constant B_0 : STD_LOGIC := '1';
        constant B_1 : STD_LOGIC := '0';
        begin

     for i in 0 to 15 loop
             if (i = 0) then
                two_s_complement ( A(i), B_0 ,temp_C(i) ,temp_Cout(i) , B_1);
             else
                two_s_complement ( A(i), B_1 ,temp_C(i) ,temp_Cout(i) , temp_C(i-1));
             end if;

     end loop;
     Cout <= temp_Cout;
    end process;

end Behavioral;

测试台：

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity two_s_complement_16bit_rtl_tb is
end;

architecture bench of two_s_complement_16bit_rtl_tb is

  component two_s_complement_16bit_rtl
      Port ( A : in  STD_LOGIC_VECTOR (15 downto 0);
             Cout : out  STD_LOGIC_VECTOR (15 downto 0):= (others => '0'));
  end component;

  signal A: STD_LOGIC_VECTOR (15 downto 0);
  signal Cout: STD_LOGIC_VECTOR (15 downto 0):= (others => '0');

begin

  uut: two_s_complement_16bit_rtl port map ( A    => A,
                                             Cout => Cout );

  stimulus: process
  begin


    -- Put initialisation code here
  A <= "0100010010110000";
  wait for 10 ns;

  A <= "0011000011110111";
  wait for 10 ns;

  A <= "0000000000000001";
  wait for 10 ns;

  A <= "0011110010110011";
  wait for 10 ns;

  A <= "0010000100100001";
  wait for 10 ns;

  A <= "0001011100100011";
  wait for 10 ns;

  A <= "1011000110111001";
  wait for 10 ns;

  A <= "0000001011001010";
  wait for 10 ns;

  A <= "0011110110100000";
  wait for 10 ns;

  A <= "0100000111111000";
  wait for 10 ns;

  A <= "1011111001111100";
  wait for 10 ns;

  A <= "1111000110000001";
  wait for 10 ns;

  A <= "0111000111001011";
  wait for 10 ns;

  A <= "1011011101101010";
  wait for 10 ns;

  A <= "1111001001010111";
  wait for 10 ns;



    -- Put test bench stimulus code here
    wait;
  end process;


end;

我已经为第一个单元考虑了三个输入，但其中两个 Cin 和 B 具有代码中提到的常量值，但输出未知。

Answer 1

存在三个明显的错误。

首先，two_s_complement程序没有分配C，这很容易修复：

    procedure 
        two_s_complement  (
            a:     in  std_logic;
            b:     in  std_logic;
            c:     out std_logic;
            cout:  out std_logic;
            cin:   in  std_logic
        ) is
        variable inta: std_logic := not a;
    begin  
        c := inta xor b xor cin;    -- ADDED
        cout := ((not a) and b) xor (((not a) xor b) and cin);
        -- cout := (inta and b) or (inta and cin);
    end procedure;

这显示为一个输入反相的全加器。

其次，您在过程调用中对 cin 的关联不正确：

        for i in 0 to 15 loop
            if i = 0 then
                two_s_complement ( 
                    a    => a(i), 
                    b    => b_0,
                    c    => temp_c(i),
                    cout => temp_cout(i), 
                    cin  => b_1
                );
            else
                two_s_complement ( 
                    a    => a(i),
                    b    => b_1,
                    c    => temp_c(i),
                    cout => temp_cout(i),
                    cin  => temp_cout(i - 1) -- WAS temp_c(i-1)
                );
            end if;

当您使用命名关联时，错误很明显。

第三个 two_s_complement_16bit_rtl 的 cout 输出应该从 temp_c:

分配

        cout <= temp_c; -- WAS temp_cout;

解决这三个问题可以得到：

看起来不错的东西。

可以通过将非 A 传送到递增电路来简化二进制补码，在递增电路中所有不需要的门都被简化并消除了 B 输入。例如，您会发现 LSB 从未受到影响。

VHDL 中的程序 returns 未知

procedure in VHDL returns unknown

vhdl