Error: D:/velilog/bubu.vhd(3): near "clock_in": (vcom-1576) expecting END

Question

我正在尝试使用 modelsim 在 vhdl 中创建一个 fsm，但是当我尝试编译我的代码时，我遇到了这个错误

enter code here
entity timer_50Mhz is
    generic(count : integer range 0 to 50000000 := 2);    
        clock_in : in  STD_LOGIC;
           clock_out : out  STD_LOGIC);
end timer_50Mh
z;
architecture Behavioral of timer_50Mhz is
begin
 process(clock_in)
 variable temp :integer range 0 to 5000000 := 0; 
 begin
  if(rising_edge(clock_in)) then 
   if(temp = count-1) then
    temp :=0;
    clock_out <='1';
   else
    temp := temp + 1;
    clock_out <='0';
 end process;

end Behavioral;

如能解决，不胜感激

Answer 1

这个

entity timer_50Mhz is
    generic(count : integer range 0 to 50000000 := 2);    
        clock_in : in  STD_LOGIC;
        clock_out : out  STD_LOGIC);
end timer_50Mhz;

应该是这样的：

entity timer_50Mhz is
    generic(count : integer range 0 to 50000000 := 2);    
    port(
        clock_in : in  STD_LOGIC;
        clock_out : out  STD_LOGIC);
end timer_50Mhz;