vhdl 案例...是和...select

Question

我正在尝试在 VHDL 上写一些东西，但它不起作用。这是我的部分代码：

case currentState is
    when ST000 =>
        with A select nextState <=
            ST025 when "01",
            ST050 when "10",
            ST000 when "11",
            currentState when others;
    when ST001 => ...
    when others => ...
end case;

它说这些行有问题，像这样：Line 62. parse error, unexpected WITH。为什么这 with 出乎意料？将 case...is 和 with...select 这两种语法混合在一起是错误的吗？

Answer 1

除非另有说明，否则参考来自 IEEE Std 1076-2008，IEEE VHDL 语言参考手册。

10. Sequential statements

10.1 General

The various forms of sequential statements are described in this clause. Sequential statements are used to define algorithms for the execution of a subprogram or process; they execute in the order in which they appear.

10.9 Case statement

A case statement selects for execution one of a number of alternative sequences of statements; the chosen alternative is defined by the value of an expression.

一系列语句表示顺序语句。

10.5.4 Selected signal assignments

The selected signal assignment represents an equivalent case statement that assigns values to signals or that forces or releases signals.

然而...

Annex E
(informative)
Changes from IEEE Std 1076-2002

...
Clause 10

— 10.5: Addition of force and release assignment; addition of simple, conditional and selected signal assignment.

在早于 -2008 的 VHDL 标准修订版中，选定的信号分配仅可用作并发信号分配语句（请参阅 11.6 并发信号分配语句，或在 Clause/Chapter 9 并发语句中找到，第 9.5.2 小节VHDL 标准早期修订版中的选定信号分配）。

请注意，当不方便或不支持此 -2008 功能时，您可以用 case 语句代替：

case currentState is
    when ST000 =>
        case A is
            when "01" =>
                nextState <= ST025;
            when "10" =>
                nextState <= ST050;
            when "11" =>
                nextState <= ST000;
            when others =>
                nextState <= CurrentState;
        end case;
    when ST001 => ...
    when others => ...
end case;

vhdl 案例...是和...select

vhdl case...is and with...select

select

case

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