在 Vivado 2017.1 中模拟 VHDL 2008 无约束数组类型

Question

我有以下类型

type VECTOR_ARRAY_TYPE is array(natural range <>) of std_logic_vector;

我在我的实体中使用如下：

entity mux is

  generic (
    sel_width  : positive := 2;
    data_width : positive := 3
  );

  port (
    d   : in  VECTOR_ARRAY_TYPE(2**sel_width - 1 downto 0)(data_width - 1 downto 0);
    sel : in  std_logic_vector(sel_width - 1 downto 0);
    q   : out std_logic_vector(data_width - 1 downto 0)
  );

end mux;

我正在使用 Vivado 2017.1 并将文件标记为 VHDL 2008。这些文件合成得非常好，但是在尝试运行仿真时出现以下错误：

ERROR: [XSIM 43-4187] File "/project_dir/sources_1/new/alu_data.vhd" Line 42 : The "Vhdl 2008 Unconstrained Array Type as Subtype in Array Type Definition" is not supported yet for simulation.

它引用的行号是上面的类型定义。

是不是错误是正确的，无约束的数组类型不能用于模拟？还是我需要更改某处设置以不同方式配置模拟器？

谢谢。

Answer 1

所以你的问题是关于一个软件工具，它有大量的在线文档。所以你应该看看网站。 http://www.xilinx.com --> support --> documentation --> Development tools --> Hardware development --> Vivado Design Suite --> User Guides. Et voila: UG900 - Vivado Design Suite User Guide: Logic Simulation v2017.4

Appendix C: VHDL 2008 Support in Vivado Simulator

The Vivado® simulator supports the subset of VHDL 2008(IEEE 1076-2008). The complete list is given in Table C-1.

[partial] Table C-1:

VHDL-2008 STD and IEEE packages precompiled, including new fixed and float packages, unsigned bit etc.

Simplified sensitivity list

Matching Relational Operators

Unary Reduction Logic Operators

Simplified Case Statement

Array / Bit Logic Operators

Array / Bit Addition Operators

Enhanced Bit String Literals

Conditional and selected sequential statements

Protected type

Keyword ‘parameter’ in procedure declaration

Array element resolution function in subtype definition

Block comments

Predefined array types

Type passed as Generic

Hierarchical references to signal

Expression in port map

Reading output port

Note: Other features that are not mentioned in the above table, are not supported by Vivado Simulator.

在 Vivado 2017.1 中模拟 VHDL 2008 无约束数组类型

Simulating VHDL 2008 unconstrained array type in Vivado 2017.1

fpga

vhdl

vivado