VHDL：如何将二进制数转换为十进制数

Question

我正在通过项目学习VHDL，我想将二进制数转换为十进制数（也用二进制表示）。我需要这样做，因为我正在打印十进制数，如果我尝试打印它而不转换它，我会得到一个十六进制数...

例如我有 0010 1010 1111 0001 (2AF1)，我想要 0001 0000 1001 1001 0011 (10993)

我必须明确我的二进制数是 32 位的

一定很简单，因为我在网上找不到解决方案...

编辑：此代码正在运行并将二进制数转换为以二进制表示的十进制数 (d'10 = b'0001 0000)

    signal val0 : std_logic_vector(31 downto 0);
    signal val1 : std_logic_vector(31 downto 0);
    signal val2 : std_logic_vector(31 downto 0);
    signal val_Mux : std_logic_vector(31 downto 0);

            val_MUX <= std_logic_vector(unsigned(val0)+1) when cpt50M_Comp = '1' else val0;


    val1(3 downto 0)<= val_MUX(3 downto 0);
    loopA:
        for i in 0 to 6 generate
            val1(4*i+7 downto 4*i+4) <= std_logic_vector(unsigned(val_MUX(4*i+7 downto 4*i+4))+1) when val1(4*i+3 downto 4*i) > "1001" 
                    else val_MUX(4*i+7 downto 4*i+4);
            val2(4*i+3 downto 4*i) <= "0000" when val1(4*i+3 downto 4*i) > "1001" 
                    else val1(4*i+3 downto 4*i); 

    end generate loopA;
    val2(31 downto 28)<= val1(31 downto 28);


    val0 <= (others => '0') when reset='1' else 
        val2 when rising_edge(clk50);

Answer 1

解决方案是在分配一个显示器之前通过另外 2 个信号，并为计数器分配一个显示器，如下所示：

signal val0 : std_logic_vector(31 downto 0);
signal val1 : std_logic_vector(31 downto 0);
signal val2 : std_logic_vector(31 downto 0);
signal val_Mux : std_logic_vector(31 downto 0);

        val_MUX <= std_logic_vector(unsigned(val0)+1) when cpt50M_Comp = '1' else val0;


val1(3 downto 0)<= val_MUX(3 downto 0);
loopA:
    for i in 0 to 6 generate
        val1(4*i+7 downto 4*i+4) <= std_logic_vector(unsigned(val_MUX(4*i+7 downto 4*i+4))+1) when val1(4*i+3 downto 4*i) > "1001" 
                else val_MUX(4*i+7 downto 4*i+4);
        val2(4*i+3 downto 4*i) <= "0000" when val1(4*i+3 downto 4*i) > "1001" 
                else val1(4*i+3 downto 4*i); 

end generate loopA;
val2(31 downto 28)<= val1(31 downto 28);


val0 <= (others => '0') when reset='1' else 
    val2 when rising_edge(clk50);

VHDL：如何将二进制数转换为十进制数

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