未初始化的无符号信号

Question

遇到以下示例代码：

architecture arch of disp_mux is
  constant N:integer :=18;
  signal q_reg, q_next: unsigned(N-1 downto 0);
  signal sel: std_logic_vector(1 downto 0);
begin
  process(clk, reset)
  begin
    if reset='1' then
      q_reg <= (others=>'0');
    elsif (clk'event and clk='1') then
      q_reg <= q_next;
    end if;
  end process;
  q_next <= q_reg + 1;
  sel <= std_logic_vector(q_reg(N-1 downto N-2));
  process(sel, ...)
  begin
    case sel is...
    end case;
  end process;
end arch;

如果你从不把1写成reset，那么q_reg的值是多少？ q_next <= q_reg + 1; when/if q_reg 处发生的事情是 UUUUUUUUUUUUUUUUUU 我怀疑是这样。

Answer 1

如果你从不将 1 写入 reset，q_reg 是 "UUUUUUUUUUUUUUUUUU" 并且在执行 q_next <= q_reg + 1 之后 q_next 变为 "XXXXXXXXXXXXXXXXXX"。

未初始化的无符号信号

Unitialized unsigned signals

vhdl