逻辑电路功能和设计vhdl代码

Question

我不知道我使用卡诺表发现的这 2 个函数是否正在计算下面的 VHDL 代码（我不太擅长 VHDL）。

函数：

f <= (x3 or x5) and (x2 or x4') and (x4' or x5) and (x1' or x2) and (x2' or x4 or x5')

和

g <= (x2 or x4' or x5') and (x2 or x3' or x4') and (x2' or x4 or x5') and (x1' or x2 or x5 ') 和 (x1 或 x3' 或 x4' 或 x5')

代码如下：

basic_components.vhd :

library ieee;
use ieee.std_logic_1164.all;
package basic_components is
  -- AND2 declaration
 component myAND2
        port (in1, in2: in std_logic; out1: out std_logic);
 end component;
 -- OR2 declaration
  component myOR2
       port (in1, in2: in std_logic; out1: out std_logic);
 end component;
  --NOT1 declaration
  component myNOT1           
       port (in1: in std_logic; out1: out std_logic);
 end component;
end package basic_components;

library ieee;
use ieee.std_logic_1164.all;

 -- 2 input AND gate
 entity myAND2 is

       port (in1, in2: in std_logic; out1: out std_logic);
 end myAND2;
 architecture model_conc of myAND2 is
       begin

                 out1 <= in1 and in2;
 end model_conc;
  -- 2 input OR gate
library ieee;
use ieee.std_logic_1164.all;
  entity myOR2 is

       port (in1, in2: in std_logic; out1: out std_logic);
 end myOR2;
 architecture model_conc2 of myOR2 is
       begin

                 out1 <= in1 or in2;
 end model_conc2;
  -- 1 input NOT gate
library ieee;
use ieee.std_logic_1164.all;
  entity myNOT1 is

       port (in1: in std_logic; out1: out std_logic);
 end myNOT1;
 architecture model_conc3 of myNOT1 is
       begin

                 out1 <= not in1;
 end model_conc3;

problem1.vhd:

    library ieee, basic_components;
use ieee.std_logic_1164.all;
use work.basic_components.all;
entity Problem1 is
    port (x1, x2, x3,x4,x5: in std_logic;
    f,g: out std_logic);
end Problem1;

architecture structural of Problem1 is
signal not_x1,not_x2,not_x3,not_x4,not_x5,pos1,pos2,pos3,pos4,pos5,pos6,pos7,pos8,pos9: std_logic;

begin

I0: myNOT1 port map(x1,not_x1);
I1: myNOT1 port map(x2,not_x2);
I2: myNOT1 port map(x3,not_x3);
I3: myNOT1 port map(x4,not_x4);
I4: myNOT1 port map(x5,not_x5);
I5: myOR2 port map(x2,not_x4,pos1);
I6: myOR2 port map(x3,x5,pos2);
I7: myOR2 port map(not_x4,x5,pos3);
I8: myOR2 port map(not_x1,x2,pos4);
I9: myOR3 port map(not_x2,x4,not_x5,pos5);
I10: myOR3 port map(not_x2,not_x4,not_x5,pos6);
I11: myOR3 port map(x2,not_x3,not_x4,pos7);
I12: myOR3 port map(not_x1,x2,not_x5,pos8);
I13: myOR4 port map(not_x1,not_x3,not_x4,x5,pos9);
I14: myAND5 port map(pos1,pos2,pos3,pos4,pos5,f);
I15:myAND5 port map(pos5,pos6,pos7,pos8,pos9,g);

end structural;

Answer 1

正如您post中的评论所说，这种编写VHDL的方式不是"practical"。但是你可以用更好的方式写出你的方程式，compile/simulate 同时比较两个结果。

library ieee, basic_components;
  use ieee.std_logic_1164.all;
  use work.basic_components.all;

entity Problem1 is
    port (x1, x2, x3,x4,x5: in std_logic;
    f,g: out std_logic);
end Problem1;

architecture structural of Problem1 is
signal not_x1,not_x2,not_x3,not_x4,not_x5,pos1,pos2,pos3,pos4,pos5,pos6,pos7,pos8,pos9,f1,f2,g1,g2: std_logic;

begin
-- First equations the way VHDL is meaned to be used
f1 <= (x3 or x5) and (x2 or not x4) and (not x4 or x5) and (not x1 or x2) and (not x2 or x4 or not x5);
g1 <= (x2 or not x4 or not x5) and (x2 or not x3 or not x4) and (not x2 or x4 or not x5) and (not x1 or x2 or not x5) and (x1 or not x3 or not x4 or not x5);

-- Second equations, your school problem
I0: myNOT1 port map(x1,not_x1);
I1: myNOT1 port map(x2,not_x2);
I2: myNOT1 port map(x3,not_x3);
I3: myNOT1 port map(x4,not_x4);
I4: myNOT1 port map(x5,not_x5);
I5: myOR2 port map(x2,not_x4,pos1);
I6: myOR2 port map(x3,x5,pos2);
I7: myOR2 port map(not_x4,x5,pos3);
I8: myOR2 port map(not_x1,x2,pos4);
I9: myOR3 port map(not_x2,x4,not_x5,pos5);
I10: myOR3 port map(not_x2,not_x4,not_x5,pos6);
I11: myOR3 port map(x2,not_x3,not_x4,pos7);
I12: myOR3 port map(not_x1,x2,not_x5,pos8);
I13: myOR4 port map(not_x1,not_x3,not_x4,x5,pos9);
I14: myAND5 port map(pos1,pos2,pos3,pos4,pos5,f2);  -- Here, f is replaced by f2 
I15:myAND5 port map(pos5,pos6,pos7,pos8,pos9,g2);  -- Here, g is replaced by g2 

-- process for auto-test
process(f1,f2,g1,g2)
begin
  -- this will test the equation f1=f2, if wrong the simulator will stop with the message "F calcul is wrong"
  assert (f1 = f2) report "F calcul is wrong" severity failure;
  -- this will test the equation g1=g2, if wrong the simulator will stop with the message "G calcul is wrong"
  assert (g1 = g2) report "G calcul is wrong" severity failure;
end process;

-- output is linked to your school solution
f <= f2;
g <= g2;

end architecture;

现在你必须编写一个测试平台来为你的实体提供 32 个可能的输入，看看模拟器是否有任何问题。

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