请帮我解决 VHDL 编译错误
Please help me with VHDL compile error
library IEEE;
use IEEE.std_logic_1164.all;
entity doorlock is
port( reset : in std_logic;
enable : in std_logic;
password : in std_logic_vector (7 downto 0);
door : out std_logic_vector (7 downto 0);
lock : out std_logic;
alarm : out std_logic;
turnoff : out std_logic);
end doorlock;
--password is 10(decimal no.) which is 00010000(binary no.)
architecture DDL of doorlock is
signal err_count : integer range 0 to 5 := 0;
begin
lock <= '0' when (reset = '0');
alarm <= '0' when (reset = '0');
turnoff <= '0' when (reset = '0');
door <= "00000000" when (reset = '0');
lock <= '0' when (enable <= '0');
process(password)
begin
if (password = "-------1") then
door <= "00000000";
elsif (password = "------10") then
door <= "00000001";
elsif (password = "-----100") then
door <= "00000011";
elsif (password = "----1000") then
door <= "00000111";
elsif (password = "---00000") then
door <= "00001111";
elsif (password = "--110000") then
door <= "00011111";
elsif (password = "-1010000") then
door <= "00111111";
elsif (password = "10010000") then
door <= "01111111";
elsif (password = "00010000") then
door <= "11111111";
end if;
err_count <= err_count + 1;
end process;
alarm <= '1' when (err_count = 3);
turnoff <= '1' when (err_count = 5);
lock <= '1' when (door = "11111111" and turnoff = '0' and alarm = '0');
end DDL;
我为制作数字门锁的作业编写了这段代码。
这行在我编译时有错误。
lock <= '1' when (door = "11111111" and turnoff = '0' and alarm = '0');
错误如下
** 错误：D:\modelsim\Door.vhd(53)：无法读取输出 "alarm".
VHDL 2008 允许读取输出。
通过使用 -2008 编译启用此功能。
** 错误：D:\modelsim\Door.vhd(53)：无法读取输出 "door".
VHDL 2008 允许读取输出。
通过使用 -2008 编译启用此功能。
** 错误：D:\modelsim\Door.vhd(53)：无法读取输出 "turnoff".
VHDL 2008 允许读取输出。
通过使用 -2008 编译启用此功能。
** 错误：D:\modelsim\Door.vhd(55): VHDL 编译器正在退出
我不知道为什么会这样，请帮助我
首先："Please help me" 不是一个好问题。更好的做法是 "Modelsim error "编译时无法读取输出”
第二次：错误描述性很强。 "Cannot read output "报警“”。 alarm 声明为
alarm : out std_logic;
因此它是一个输出端口。在 2008 年之前的 VHDL 中，不允许读取输出端口。接下来编译器提示如何修复它：
"VHDL 2008 allows reading outputs. This facility is enabled by compiling with -2008."
那就这样做吧！
在你的modelsim编译中 window select "default options"
然后设置为VHDL-2008
或者，您实际上可以在命令行上执行所描述的操作（添加 -2008）：
vcom -reportprogress 300 -work work -2008 doorlock.vhd
瞧。完成的！不是吗？
等一下，还是不行！
您有多个驱动程序错误。第 23 行指出：
door <= "00000000" when (reset = '0');
这作为一个闩锁，实际上与
相同
process(reset) begin
if reset = '0' then
door <= "00000000";
end if;
end process;
因此，一旦 reset='0' 发生，该过程会将 door 驱动为固定值。在 password 触发的过程中，您再次驱动 door！这将解决不好。例如。如果 (password = "------10")，则 door <= "00000001"。这将解决：
resolve("00000000", "00000001") = "0000000X"
因为'0'接'1'相当于短路
让我们看看正确的设计。您现在正在触发 password 的更改。不太好，但这是可能的。我会使用另一个触发器，例如未使用的 enable 信号。但无论如何：我们引入了一个额外的信号来检测变化 password_delay。但更重要的是 我们引入了一个时钟 。在数字硬件中，大多数系统都使用时钟。最后，我们使用新的 VHDL-2008 语句 case? 来解码 don't cares.
VHDL-2008 代码一起变成：
library IEEE;
use IEEE.std_logic_1164.all;
entity doorlock is
port(
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
password : in std_logic_vector (7 downto 0);
door : out std_logic_vector (7 downto 0);
lock : out std_logic;
alarm : out std_logic;
turnoff : out std_logic
);
end doorlock;
--password is 10(decimal no.) which is 00010000(binary no.)
architecture DDL of doorlock is
signal password_delay : std_logic_vector(password'range) := password;
use ieee.numeric_std_unsigned.all;
signal err_count : integer range 0 to 5 := 0;
begin
clk_proc : process(clk) begin
if rising_edge(clk) then
if reset = '0' then
door <= (others => '0');
lock <= '0';
alarm <= '0';
turnoff <= '0';
err_count <= 0;
else -- no reset :)
if password /= password_delay then
case? password is
when "-------1" => door <= "00000000";
when "------10" => door <= "00000001";
when "-----100" => door <= "00000011";
when "----1000" => door <= "00000111";
when "---00000" => door <= "00001111";
when "--110000" => door <= "00011111";
when "-1010000" => door <= "00111111";
when "10010000" => door <= "01111111";
when "00010000" => door <= "11111111";
when others => null;
end case?;
err_count <= err_count + 1;
end if;
case err_count is
when 3 => alarm <= '1';
when 5 => turnoff <= '1';
when others => null;
end case;
if door = "11111111" and turnoff = '0' and alarm = '0' then
lock <= '1';
end if;
end if;
password_delay <= password;
end if;
end process;
end DDL;
这是不一样的，嗯？很抱歉，我没有时间给你写一个测试平台。
注意：代码给出编译器警告
Warning: C:/HDL/doorlock/doorlock.vhd(20): (vcom-1013) Initial value of "password_delay" depends on value of signal "password".
忽略这个。这是模拟所必需的，否则 password_delay 的未定义初始值将导致 password /= password_delay.
的触发
library IEEE;
use IEEE.std_logic_1164.all;
entity doorlock is
port( reset : in std_logic;
enable : in std_logic;
password : in std_logic_vector (7 downto 0);
door : out std_logic_vector (7 downto 0);
lock : out std_logic;
alarm : out std_logic;
turnoff : out std_logic);
end doorlock;
--password is 10(decimal no.) which is 00010000(binary no.)
architecture DDL of doorlock is
signal err_count : integer range 0 to 5 := 0;
begin
lock <= '0' when (reset = '0');
alarm <= '0' when (reset = '0');
turnoff <= '0' when (reset = '0');
door <= "00000000" when (reset = '0');
lock <= '0' when (enable <= '0');
process(password)
begin
if (password = "-------1") then
door <= "00000000";
elsif (password = "------10") then
door <= "00000001";
elsif (password = "-----100") then
door <= "00000011";
elsif (password = "----1000") then
door <= "00000111";
elsif (password = "---00000") then
door <= "00001111";
elsif (password = "--110000") then
door <= "00011111";
elsif (password = "-1010000") then
door <= "00111111";
elsif (password = "10010000") then
door <= "01111111";
elsif (password = "00010000") then
door <= "11111111";
end if;
err_count <= err_count + 1;
end process;
alarm <= '1' when (err_count = 3);
turnoff <= '1' when (err_count = 5);
lock <= '1' when (door = "11111111" and turnoff = '0' and alarm = '0');
end DDL;
我为制作数字门锁的作业编写了这段代码。 这行在我编译时有错误。
lock <= '1' when (door = "11111111" and turnoff = '0' and alarm = '0');
错误如下
** 错误：D:\modelsim\Door.vhd(53)：无法读取输出 "alarm".
VHDL 2008 允许读取输出。 通过使用 -2008 编译启用此功能。
** 错误：D:\modelsim\Door.vhd(53)：无法读取输出 "door".
VHDL 2008 允许读取输出。 通过使用 -2008 编译启用此功能。
** 错误：D:\modelsim\Door.vhd(53)：无法读取输出 "turnoff".
VHDL 2008 允许读取输出。 通过使用 -2008 编译启用此功能。
** 错误：D:\modelsim\Door.vhd(55): VHDL 编译器正在退出
我不知道为什么会这样，请帮助我
首先："Please help me" 不是一个好问题。更好的做法是 "Modelsim error "编译时无法读取输出”
第二次：错误描述性很强。 "Cannot read output "报警“”。 alarm 声明为
alarm : out std_logic;
因此它是一个输出端口。在 2008 年之前的 VHDL 中，不允许读取输出端口。接下来编译器提示如何修复它：
"VHDL 2008 allows reading outputs. This facility is enabled by compiling with -2008."
那就这样做吧！ 在你的modelsim编译中 window select "default options"
然后设置为VHDL-2008
或者，您实际上可以在命令行上执行所描述的操作（添加 -2008）：
vcom -reportprogress 300 -work work -2008 doorlock.vhd
瞧。完成的！不是吗？
等一下，还是不行！
您有多个驱动程序错误。第 23 行指出：
door <= "00000000" when (reset = '0');
这作为一个闩锁，实际上与
相同process(reset) begin
if reset = '0' then
door <= "00000000";
end if;
end process;
因此，一旦 reset='0' 发生，该过程会将 door 驱动为固定值。在 password 触发的过程中，您再次驱动 door！这将解决不好。例如。如果 (password = "------10")，则 door <= "00000001"。这将解决：
resolve("00000000", "00000001") = "0000000X"
因为'0'接'1'相当于短路
让我们看看正确的设计。您现在正在触发 password 的更改。不太好，但这是可能的。我会使用另一个触发器，例如未使用的 enable 信号。但无论如何：我们引入了一个额外的信号来检测变化 password_delay。但更重要的是 我们引入了一个时钟 。在数字硬件中，大多数系统都使用时钟。最后，我们使用新的 VHDL-2008 语句 case? 来解码 don't cares.
VHDL-2008 代码一起变成：
library IEEE;
use IEEE.std_logic_1164.all;
entity doorlock is
port(
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
password : in std_logic_vector (7 downto 0);
door : out std_logic_vector (7 downto 0);
lock : out std_logic;
alarm : out std_logic;
turnoff : out std_logic
);
end doorlock;
--password is 10(decimal no.) which is 00010000(binary no.)
architecture DDL of doorlock is
signal password_delay : std_logic_vector(password'range) := password;
use ieee.numeric_std_unsigned.all;
signal err_count : integer range 0 to 5 := 0;
begin
clk_proc : process(clk) begin
if rising_edge(clk) then
if reset = '0' then
door <= (others => '0');
lock <= '0';
alarm <= '0';
turnoff <= '0';
err_count <= 0;
else -- no reset :)
if password /= password_delay then
case? password is
when "-------1" => door <= "00000000";
when "------10" => door <= "00000001";
when "-----100" => door <= "00000011";
when "----1000" => door <= "00000111";
when "---00000" => door <= "00001111";
when "--110000" => door <= "00011111";
when "-1010000" => door <= "00111111";
when "10010000" => door <= "01111111";
when "00010000" => door <= "11111111";
when others => null;
end case?;
err_count <= err_count + 1;
end if;
case err_count is
when 3 => alarm <= '1';
when 5 => turnoff <= '1';
when others => null;
end case;
if door = "11111111" and turnoff = '0' and alarm = '0' then
lock <= '1';
end if;
end if;
password_delay <= password;
end if;
end process;
end DDL;
这是不一样的，嗯？很抱歉，我没有时间给你写一个测试平台。
注意：代码给出编译器警告
Warning: C:/HDL/doorlock/doorlock.vhd(20): (vcom-1013) Initial value of "password_delay" depends on value of signal "password".
忽略这个。这是模拟所必需的，否则 password_delay 的未定义初始值将导致 password /= password_delay.