结构环形振荡器 VHDL

Question

我在使用以下环形振荡器代码时遇到问题：

entity OSCILLATOR is
    port(   OUTPUT: out std_logic
    );
end entity OSCILLATOR;

architecture structural of OSCILLATOR is

component DEL_INV is
    generic(D: time);   
    port(   INPUT: in std_logic;
            OUTPUT: out std_logic   
        );
end component DEL_INV;

signal conn: std_logic := '0';
signal conn1: std_logic := '1';
signal conn2: std_logic := '0';
signal de: time := 2 ns;

begin
    INV1: DEL_INV generic map(de) port map (conn, conn1);
    INV2: DEL_INV generic map(de) port map (conn1, conn2);
    INV3: DEL_INV generic map(de) port map (conn2, conn);

    OUTPUT <= conn;

end architecture;

特别是，在模拟它时，输出始终是U。有人可以解释为什么吗？

Answer 1

分配给信号 conn* 的初始值，以确保模拟中明确定义的开始条件，在开始时被 OUTPUT 驱动的 'U' 覆盖 DEL_INV 模块，因此模拟最终卡在所有 U.

一个解决方案是通过 DEL_INV 模块使用允许不同初始 OUTPUT 值的泛型来处理初始值，然后在 OUTPUT 上使用这个初始值，直到值定义为 '0' 或 '1'，可通过 is_x 函数检测。

更新后的代码如下所示。请注意，我在 DEL_INV.

中添加了 Renaud Pacalet 对 for all: DEL_INV use entity work.DEL_INV(s); 和逆变器 (not) 的建议

library ieee;
use ieee.std_logic_1164.all;

entity DEL_INV is
  generic(
    D: time;
    XOUT: std_logic);
  port(
    INPUT: in std_logic;
    OUTPUT: out std_logic);
end entity DEL_INV;

architecture s of DEL_INV is
  signal PRE : std_logic;
begin
  PRE <= (not INPUT) after D;
  OUTPUT <= XOUT when is_x(PRE) else PRE;  -- Drive XOUT if is_x to clean up
end architecture s;


library ieee;
use ieee.std_logic_1164.all;

entity OSCILLATOR is
  port(
    OUTPUT: out std_logic);
end entity OSCILLATOR;

architecture structural of OSCILLATOR is

component DEL_INV is
  generic(
    D: time;
    XOUT: std_logic);
  port(
    INPUT: in std_logic;
    OUTPUT: out std_logic);
end component DEL_INV;

for all: DEL_INV use entity work.DEL_INV(s);

signal conn  : std_logic;
signal conn1 : std_logic;
signal conn2 : std_logic;

constant DE : time := 2 ns;

begin

    INV1: DEL_INV generic map(de, '0') port map (conn, conn1);
    INV2: DEL_INV generic map(de, '1') port map (conn1, conn2);
    INV3: DEL_INV generic map(de, '0') port map (conn2, conn);

    OUTPUT <= conn;

end architecture;

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