Error (10500): VHDL syntax error------expecting "(", or an identifier ("others" is a reserved keyword), or unary operator

Question

谁能看出我的代码有什么问题？

我是从教科书上复制代码的，但是有一些错误是教科书上没有的。

错误如下：

library IEEE;
use IEEE.std_logic_1164.all;

entity Moore_State is
port(
    CLK: in STD_LOGIC;
    S: in STD_LOGIC;
    FB: in STD_LOGIC;
    BACK_OUT: out STD_LOGIC;
    FORWARD_OUT: out STD_LOGIC
    );
end Moore_State;

architecture Moore1_arch of Moore_State is
type StateType is (idle,ready,back,forward);
signal state:StateType;
begin
Process(CLK)
begin
if(CLK'event and CLK='1') then

case state is

when idle=>
        if S='1' then state<=ready;
        else state<=idle;
        end if;
when ready=>
        if FB='0' then state<=back;
        else state<=forward;
        end if;
when back=>
        if S='1' then state<=idle;
        else state<=back;
        end if;
when forward=>
        if S='1' then state<=idle;
        else state<=forward;
        end if;

        end case;
    end if;
end Process;

with state select
    BACK_OUT <='1' when back,
            '0' when others;
    FORWARD_OUT <='1' when forward,
            '0' when others;

end Moore1_arch;

错误信息出现在最后一段：

1.Error (10500): VHDL1.vhd(48) 文本“,”附近的 VHDL 语法错误；期待“;”

2.Error (10500): VHDL1.vhd(49) 文本附近的 VHDL 语法错误 "others"；期望“(”，或标识符（"others" 是保留关键字），或一元运算符

Answer 1

你忘记了第二部分的with-select语句：

with state select
    BACK_OUT     <= '1' when back,
                    '0' when others;

with state select
    FORWARD_OUT  <= '1' when forward,
                    '0' when others;

Error (10500): VHDL syntax error------expecting "(", or an identifier ("others" is a reserved keyword), or unary operator

Error (10500): VHDL syntax error------expecting "(", or an identifier ("others" is a reserved keyword), or unary operator

vhdl