std_logic_vector 的 VHDL 乘法

Question

在仿真的时候，出现了运行时间错误，所以我尝试在Vivado中运行进行RTL分析，看看能否至少创建出元件的原理图。我的代码如下：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity multiplicator_test is
    generic(
            WORD_SIZE: natural := 8;
            EXP_SIZE: natural := 3
        );
        port(
            input_1: in std_logic_vector(WORD_SIZE-1 downto 0);
            input_2: in std_logic_vector(WORD_SIZE-1 downto 0);
            result: out std_logic_vector(WORD_SIZE-1 downto 0)
        );
end entity multiplicator_test;

architecture multiplicator_test_arch of multiplicator_test is
    constant SIGNIFICAND_SIZE: natural := WORD_SIZE - EXP_SIZE - 1;

    signal significand: std_logic_vector(SIGNIFICAND_SIZE-1 downto 0) := (others => '0');
    signal exponent: std_logic_vector(EXP_SIZE-1 downto 0) := (others => '0');
    signal sign: std_logic := '0';
    signal aux: std_logic_vector((2*SIGNIFICAND_SIZE)-1 downto 0) := (others => '0');
begin
        aux <= std_logic_vector(signed(input_1(SIGNIFICAND_SIZE-1 downto 0))*signed(input_2(SIGNIFICAND_SIZE - 1 downto 0)));
        significand <= aux(SIGNIFICAND_SIZE - 1 downto 0);
        exponent <= std_logic_vector(unsigned(input_1(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2))+unsigned(input_2(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2)));
        sign <= input_1(WORD_SIZE-1) or input_2(WORD_SIZE-1);
        result <= sign & exponent & significand;
end architecture multiplicator_test_arch;

当运行分析时，我得到：

ERROR: [Synth 8-690] width mismatch in assignment; target has 3 bits, source has 4 bits [(...)/multiplicador.vhd:27]

错误的行是27：

aux <= std_logic_vector(signed(input_1(SIGNIFICAND_SIZE-1 downto 0))*signed(input_2(SIGNIFICAND_SIZE - 1 downto 0)));

貌似目标（aux）是3位，但实际上应该是8位。

Answer 1

您发布的行不是第 27 行，第 27 行如下：

exponent <= std_logic_vector(unsigned(input_1(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2))+unsigned(input_2(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2)));

如你所见，指数只有3位：

无符号加法需要一个额外的位来进位。基本上，乘法运算可能会溢出。

解决这个问题的一种方法是将结果和指数加宽一点：

result: out std_logic_vector(WORD_SIZE downto 0)
signal exponent: std_logic_vector(EXP_SIZE downto 0) := (others => '0');

产量：

std_logic_vector 的 VHDL 乘法

VHDL multiplication for std_logic_vector

multiplication

vhdl