比较赋值给 std_logic_vector 的整数值
Comparing integer values for assignment to a std_logic_vector
我有一个范围为 0 到 23 的整数数组，它存储范围为 0 到 2 的值
例如：
type t_slave_24symbol is array (0 to 23) of integer range 0 to 2;
signal slave_24symbol : t_slave_24symbol;
type nibble_array is array (0 to 7) of STD_LOGIC_VECTOR(3 downto 0);
signal nibble : nibble_array;
signal nibble_full : STD_LOGIC_VECTOR(31 downto 0) := "00000000000000000000000000000000";
现在我想将这个字符串拆分为 3 个序列并进行比较
nibble(0) <= "0000" when slave_24symbol(012) = 120 else--
"0001" when slave_24symbol(012)= 200 else
"0010" when slave_24symbol(012)= 020 else
"1111";
但后来
nibble(3) <= "0000" when slave_24symbol(91011) = 012 else
。
.
.
最后
nibble_full <= nibble(0) & nibble(1) & nibble(2) & nibble(3) & nibble(4)
& nibble(5) & nibble(6) & nibble(7);
我该怎么做？因为我想分配 char 9 10 和 11 等等。
题目表现python语法思维。
std_logic_vector 数组中有一个约束整数数组被转换为二进制表示。
首先是一个有效的 Minimal, Complete, and Verifiable example 用于分配半字节的一个元素：
library ieee;
use ieee.std_logic_1164.all;
entity depython is
end entity;
architecture foo of depython is
type t_slave_24symbol is array (natural range <>) of integer range 0 to 2;
signal slave_24symbol: t_slave_24symbol (0 to 23);
type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0);
signal nibble: nibble_array;
signal nibble_full: std_logic_vector(31 downto 0) := (others => '0');
subtype nyyblet is t_slave_24symbol (0 to 2);
begin
-- nibble(0) <= "0000" when slave_24symbol(012) = 120 else--
-- "0001" when slave_24symbol(012)= 200 else
-- "0010" when slave_24symbol(012)= 020 else
-- "1111";
-- BECOMES:
nibble(0) <= "0000" when slave_24symbol(0 to 2) = nyyblet'(1, 2, 0) else
"0001" when slave_24symbol(0 to 2) = nyyblet'(2, 0, 0) else
"0010" when slave_24symbol(0 to 2) = nyyblet'(0, 2, 0) else
"1111";
end architecture;
类型 t_slave_24symbol 已更改为无约束数组定义，信号 slave_24symbol 的声明提供子类型。 （这在 -2008 中称为无界数组定义）。
slave_24symbol 切片的索引范围更改为 VHDL 语法。在每个条件中评估的表达式的值范围已更改为使用聚合的 VHDL 语法，其类型由需要子类型定义的合格表达式提供。子类型声明需要 unconstrained/unbounded 数组定义。
需要限定表达式来指定子类型，因为数组类型的预定义相等运算符对不受约束的操作数进行运算 - 您可以测试两个不同长度数组的相等性，它们将始终不相等。 （在处理空数组时派上用场）。
请注意，字符串文字的类型（例如“0010”）由上下文决定，元素值（'0'、'1'）必须与元素类型兼容（此处std_ulogic）数组类型（这里是std_logic_vector）。
本文分析、阐述和模拟（对slave_24symbol的每个元素使用默认值（0,0,0），每个进程在初始化时执行一次，并发赋值语句阐述为等价过程语句中包含顺序赋值语句）。
现在我们解决如何在新架构中转换 nibble 的所有元素：
architecture sequential of depython is
type t_slave_24symbol is array (natural range <>) of integer range 0 to 2;
signal slave_24symbol: t_slave_24symbol (0 to 23);
type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0);
signal nibble: nibble_array;
signal nibble_full: std_logic_vector(31 downto 0) := (others => '0');
subtype nyyblet is t_slave_24symbol (0 to 2);
function nybble (nyb: nyyblet) return std_logic_vector is
-- retv: std_logic_vector(3 downto 0);
begin
if nyb = nyyblet'(1, 2, 0) then
return "0000";
elsif nyb = nyyblet'(2, 0, 0) then
return "0001";
elsif nyb = nyyblet'(0, 2, 0) then
return "0010";
else
return "1111";
end if;
end function;
begin
-- nibble(0) <= "0000" when slave_24symbol(0 to 2) = nyyblet'(1,2,0) else
-- "0001" when slave_24symbol(0 to 2) = nyyblet'(2,0,0) else
-- "0010" when slave_24symbol(0 to 2) = nyyblet'(0,2,0) else
-- "1111";
-- but later
--
-- nibble(3) <= "0000" when slave_24symbol(91011) = 012 else
--
-- . . .
--
-- and at the end
--
-- nibble_full <= nibble(0) & nibble(1) & nibble(2) & nibble(3) & nibble(4)
-- & nibble(5) & nibble(6) & nibble(7);
process (slave_24symbol)
begin
for i in nibble'range loop
nibble(i) <= nybble(slave_24symbol(3 * i to 2 + i * 3));
end loop;
end process;
end architecture;
这里使用函数调用来隐藏一些复杂性。循环语句中的顺序赋值语句（顺序语句本身）使用偏移算法来寻址正在评估的 slave_24symbol 的三个约束整数的所有八个切片。
并且因为问题显示在条件信号赋值（此处为并发信号赋值）中赋值一个半字节元素，所以使用生成语句的并发赋值版本：
architecture concurrent of depython is
type t_slave_24symbol is array (natural range <>) of integer range 0 to 2;
signal slave_24symbol: t_slave_24symbol (0 to 23);
type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0);
signal nibble: nibble_array;
signal nibble_full: std_logic_vector(31 downto 0) := (others => '0');
subtype nyyblet is t_slave_24symbol (0 to 2);
function nybble (nyb: nyyblet) return std_logic_vector is
-- retv: std_logic_vector(3 downto 0);
begin
if nyb = nyyblet'(1, 2, 0) then
return "0000";
elsif nyb = nyyblet'(2, 0, 0) then
return "0001";
elsif nyb = nyyblet'(0, 2, 0) then
return "0010";
else
return "1111";
end if;
end function;
begin
-- process (slave_24symbol)
-- begin
-- for i in nibble'range loop
-- nibble(i) <= nybble(slave_24symbol(3 * i to 2 + i * 3));
-- end loop;
-- end process;
NIBBLE_IT:
for i in nibble'range generate
nibble(i) <= nybble(slave_24symbol(3 * i to 2 + i * 3));
end generate;
end architecture;
所有显示的架构都分析、阐述和模拟演示所有索引和切片都在子类型范围内。
请注意，您还可以将循环语句注入参数类型为 t_slave_24symbol 的函数中，并同时或顺序执行一个赋值。这也将允许检测不是由 3 个整数的倍数组成的参数值（因为类型 t_slave_24symbol 被声明为 unconstrained/unbounded）。可以通过声明新类型并创建新类型的 t_slave_24symbol 和 nyyblet 子类型来避免任何参数值检测：
architecture all_in_one_function of depython is
type c_integer_array is array (natural range <>) of integer range 0 to 2;
subtype t_slave_24symbol is c_integer_array (0 to 23);
signal slave_24symbol: t_slave_24symbol := (
1,2,0, 2,0,0, 0,2,0, 0,0,0, 0,0,1, 0,0,2, 0,1,0, 0,1,1);
signal nibble_full: std_logic_vector (31 downto 0);
function nybble (slave: t_slave_24symbol) return std_logic_vector is
type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0);
variable nib: nibble_array;
subtype nyyblet is c_integer_array (0 to 2);
begin
for i in nib'range loop
if slave(3 * i to 2 + i * 3) = nyyblet'(1, 2, 0) then
nib(i) := "0000";
elsif slave(3 * i to 2 + i * 3) = nyyblet'(2, 0, 0) then
nib(i) := "0001";
elsif slave(3 * i to 2 + i * 3) = nyyblet'(0, 2, 0) then
nib(i) := "0010";
else
nib(i) := "1111";
end if;
end loop;
return nib(0) & nib(1) & nib(2) & nib(3) &
nib(4) & nib(5) & nib(5) & nib(7);
end function;
function to_string (inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end function;
begin
NIBBLE_IT:
nibble_full <= nybble(slave_24symbol);
process
begin
wait for 0 ns;
report "nibble_full = " & to_string (nibble_full);
wait;
end process;
end architecture;
添加了 to_string 函数以兼容早于 -2008 的 VHDL 修订版。初始化信号_slave_24symbol，说明转换成功：
/usr/local/bin/ghdl -a depython1.vhdl
/usr/local/bin/ghdl -e depython
/usr/local/bin/ghdl -r depython
depython1.vhdl:79:9:@0ms:(report note): nibble_full = 00000001001011111111111111111111
我有一个范围为 0 到 23 的整数数组，它存储范围为 0 到 2 的值 例如：
type t_slave_24symbol is array (0 to 23) of integer range 0 to 2;
signal slave_24symbol : t_slave_24symbol;
type nibble_array is array (0 to 7) of STD_LOGIC_VECTOR(3 downto 0);
signal nibble : nibble_array;
signal nibble_full : STD_LOGIC_VECTOR(31 downto 0) := "00000000000000000000000000000000";
现在我想将这个字符串拆分为 3 个序列并进行比较
nibble(0) <= "0000" when slave_24symbol(012) = 120 else--
"0001" when slave_24symbol(012)= 200 else
"0010" when slave_24symbol(012)= 020 else
"1111";
但后来
nibble(3) <= "0000" when slave_24symbol(91011) = 012 else
。 . .
最后
nibble_full <= nibble(0) & nibble(1) & nibble(2) & nibble(3) & nibble(4)
& nibble(5) & nibble(6) & nibble(7);
我该怎么做？因为我想分配 char 9 10 和 11 等等。
题目表现python语法思维。
std_logic_vector 数组中有一个约束整数数组被转换为二进制表示。
首先是一个有效的 Minimal, Complete, and Verifiable example 用于分配半字节的一个元素：
library ieee;
use ieee.std_logic_1164.all;
entity depython is
end entity;
architecture foo of depython is
type t_slave_24symbol is array (natural range <>) of integer range 0 to 2;
signal slave_24symbol: t_slave_24symbol (0 to 23);
type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0);
signal nibble: nibble_array;
signal nibble_full: std_logic_vector(31 downto 0) := (others => '0');
subtype nyyblet is t_slave_24symbol (0 to 2);
begin
-- nibble(0) <= "0000" when slave_24symbol(012) = 120 else--
-- "0001" when slave_24symbol(012)= 200 else
-- "0010" when slave_24symbol(012)= 020 else
-- "1111";
-- BECOMES:
nibble(0) <= "0000" when slave_24symbol(0 to 2) = nyyblet'(1, 2, 0) else
"0001" when slave_24symbol(0 to 2) = nyyblet'(2, 0, 0) else
"0010" when slave_24symbol(0 to 2) = nyyblet'(0, 2, 0) else
"1111";
end architecture;
类型 t_slave_24symbol 已更改为无约束数组定义，信号 slave_24symbol 的声明提供子类型。 （这在 -2008 中称为无界数组定义）。
slave_24symbol 切片的索引范围更改为 VHDL 语法。在每个条件中评估的表达式的值范围已更改为使用聚合的 VHDL 语法，其类型由需要子类型定义的合格表达式提供。子类型声明需要 unconstrained/unbounded 数组定义。
需要限定表达式来指定子类型，因为数组类型的预定义相等运算符对不受约束的操作数进行运算 - 您可以测试两个不同长度数组的相等性，它们将始终不相等。 （在处理空数组时派上用场）。
请注意，字符串文字的类型（例如“0010”）由上下文决定，元素值（'0'、'1'）必须与元素类型兼容（此处std_ulogic）数组类型（这里是std_logic_vector）。
本文分析、阐述和模拟（对slave_24symbol的每个元素使用默认值（0,0,0），每个进程在初始化时执行一次，并发赋值语句阐述为等价过程语句中包含顺序赋值语句）。
现在我们解决如何在新架构中转换 nibble 的所有元素：
architecture sequential of depython is
type t_slave_24symbol is array (natural range <>) of integer range 0 to 2;
signal slave_24symbol: t_slave_24symbol (0 to 23);
type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0);
signal nibble: nibble_array;
signal nibble_full: std_logic_vector(31 downto 0) := (others => '0');
subtype nyyblet is t_slave_24symbol (0 to 2);
function nybble (nyb: nyyblet) return std_logic_vector is
-- retv: std_logic_vector(3 downto 0);
begin
if nyb = nyyblet'(1, 2, 0) then
return "0000";
elsif nyb = nyyblet'(2, 0, 0) then
return "0001";
elsif nyb = nyyblet'(0, 2, 0) then
return "0010";
else
return "1111";
end if;
end function;
begin
-- nibble(0) <= "0000" when slave_24symbol(0 to 2) = nyyblet'(1,2,0) else
-- "0001" when slave_24symbol(0 to 2) = nyyblet'(2,0,0) else
-- "0010" when slave_24symbol(0 to 2) = nyyblet'(0,2,0) else
-- "1111";
-- but later
--
-- nibble(3) <= "0000" when slave_24symbol(91011) = 012 else
--
-- . . .
--
-- and at the end
--
-- nibble_full <= nibble(0) & nibble(1) & nibble(2) & nibble(3) & nibble(4)
-- & nibble(5) & nibble(6) & nibble(7);
process (slave_24symbol)
begin
for i in nibble'range loop
nibble(i) <= nybble(slave_24symbol(3 * i to 2 + i * 3));
end loop;
end process;
end architecture;
这里使用函数调用来隐藏一些复杂性。循环语句中的顺序赋值语句（顺序语句本身）使用偏移算法来寻址正在评估的 slave_24symbol 的三个约束整数的所有八个切片。
并且因为问题显示在条件信号赋值（此处为并发信号赋值）中赋值一个半字节元素，所以使用生成语句的并发赋值版本：
architecture concurrent of depython is
type t_slave_24symbol is array (natural range <>) of integer range 0 to 2;
signal slave_24symbol: t_slave_24symbol (0 to 23);
type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0);
signal nibble: nibble_array;
signal nibble_full: std_logic_vector(31 downto 0) := (others => '0');
subtype nyyblet is t_slave_24symbol (0 to 2);
function nybble (nyb: nyyblet) return std_logic_vector is
-- retv: std_logic_vector(3 downto 0);
begin
if nyb = nyyblet'(1, 2, 0) then
return "0000";
elsif nyb = nyyblet'(2, 0, 0) then
return "0001";
elsif nyb = nyyblet'(0, 2, 0) then
return "0010";
else
return "1111";
end if;
end function;
begin
-- process (slave_24symbol)
-- begin
-- for i in nibble'range loop
-- nibble(i) <= nybble(slave_24symbol(3 * i to 2 + i * 3));
-- end loop;
-- end process;
NIBBLE_IT:
for i in nibble'range generate
nibble(i) <= nybble(slave_24symbol(3 * i to 2 + i * 3));
end generate;
end architecture;
所有显示的架构都分析、阐述和模拟演示所有索引和切片都在子类型范围内。
请注意，您还可以将循环语句注入参数类型为 t_slave_24symbol 的函数中，并同时或顺序执行一个赋值。这也将允许检测不是由 3 个整数的倍数组成的参数值（因为类型 t_slave_24symbol 被声明为 unconstrained/unbounded）。可以通过声明新类型并创建新类型的 t_slave_24symbol 和 nyyblet 子类型来避免任何参数值检测：
architecture all_in_one_function of depython is
type c_integer_array is array (natural range <>) of integer range 0 to 2;
subtype t_slave_24symbol is c_integer_array (0 to 23);
signal slave_24symbol: t_slave_24symbol := (
1,2,0, 2,0,0, 0,2,0, 0,0,0, 0,0,1, 0,0,2, 0,1,0, 0,1,1);
signal nibble_full: std_logic_vector (31 downto 0);
function nybble (slave: t_slave_24symbol) return std_logic_vector is
type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0);
variable nib: nibble_array;
subtype nyyblet is c_integer_array (0 to 2);
begin
for i in nib'range loop
if slave(3 * i to 2 + i * 3) = nyyblet'(1, 2, 0) then
nib(i) := "0000";
elsif slave(3 * i to 2 + i * 3) = nyyblet'(2, 0, 0) then
nib(i) := "0001";
elsif slave(3 * i to 2 + i * 3) = nyyblet'(0, 2, 0) then
nib(i) := "0010";
else
nib(i) := "1111";
end if;
end loop;
return nib(0) & nib(1) & nib(2) & nib(3) &
nib(4) & nib(5) & nib(5) & nib(7);
end function;
function to_string (inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end function;
begin
NIBBLE_IT:
nibble_full <= nybble(slave_24symbol);
process
begin
wait for 0 ns;
report "nibble_full = " & to_string (nibble_full);
wait;
end process;
end architecture;
添加了 to_string 函数以兼容早于 -2008 的 VHDL 修订版。初始化信号_slave_24symbol，说明转换成功：
/usr/local/bin/ghdl -a depython1.vhdl
/usr/local/bin/ghdl -e depython
/usr/local/bin/ghdl -r depython
depython1.vhdl:79:9:@0ms:(report note): nibble_full = 00000001001011111111111111111111