从不同的测试平台调用任务 systemverilog

Calling tasks from different testbenches systemverilog

我正在尝试从测试台文件调用接口文件中定义的任务。任务定义为

task master_monitor(
                   output bit [ADDR_WIDTH-1:0] addr,
                   output bit [DATA_WIDTH-1:0] data,
                   output bit we                    
                  );

          while (!cyc_o) @(posedge clk_i);                                                  
          while (!ack_i) @(posedge clk_i);
          addr = adr_o;
          we = we_o;
          if (we_o) begin
            data = dat_o;
          end else begin
            data = dat_i;
          end
          while (cyc_o) @(posedge clk_i);                                                  
     endtask 

在我的测试台中,接口被实例化为 wb_bus,我正尝试通过以下方式调用任务:

wire [WB_DATA_WIDTH-1:0] dat_wr_o;
wire [WB_DATA_WIDTH-1:0] adr;
wire we;
initial
begin
    repeat(10) begin
    wb_bus.master_monitor(adr, dat_wr_o, we);

    end
end

当我在 modelsim 上模拟这个时,我最终遇到了这些错误:

   ** Error: (vsim-3047) ../testbench/top.sv(52): actual value for formal 'data' of 'master_read' must be assignable.
#    Time: 0 ps  Iteration: 0  Instance: /top File: ../testbench/top.sv
# ** Error: (vsim-3047) ../testbench/top.sv(53): actual value for formal 'we' of 'master_monitor' must be assignable.
#    Time: 0 ps  Iteration: 0  Instance: /top File: ../testbench/top.sv
# ** Error: (vsim-3047) ../testbench/top.sv(53): actual value for formal 'data' of 'master_monitor' must be assignable.
#    Time: 0 ps  Iteration: 0  Instance: /top File: ../testbench/top.sv
# ** Error: (vsim-3047) ../testbench/top.sv(53): actual value for formal 'addr' of 'master_monitor' must be assignable.
#    Time: 0 ps  Iteration: 0  Instance: /top File: ../testbench/top.sv

我传递变量的方式是否正确?有人可以帮我吗?

您不能将 adr 之类的连线信号传递给任务的输出参数。要么将它们更改为 logic,要么创建传递给任务参数的中间变量,然后将它们 assign 传递给线路。