带同步复位的递增计数器的系统 Verilog 代码，计数到 15 并再次设置为零

Question

此逻辑是否符合系统 Verilog 准则？

always_ff (posedge CLK)

 begin 

  If (!rst)

    count <= 4'b0000;

Else

Count<= count+1'b1;

End

assign count=4'b1111 ? 4'b0000 :count;

Answer 1

下面是我将如何做到这一点。您可以免费获得环绕行为。

logic [3:0] count;

always_ff (posedge clk) begin 
  if (!rst)
    count <= 4'b0000;
  else
    count <= count+1'b1;
end

System Verilog code for upcounter with synchronous reset that counts till 15 and again sets to zero