如何写入控制台自定义数组类型
How to write to console a custom array type
我是 VHDL 的新手,我正在 运行 从我得到的代码中摘录一些代码,看看它在做什么。我想在控制台中看到一个自定义数组类型,但是当我尝试编写它时出现错误。
entity hello_world is
end entity hello_world;
library STD;
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
architecture test of hello_world is
type row_type is array(0 to 2) of std_logic_vector(3 downto 0);
type new_type is array(0 to 1) of row_type;
signal max_new : new_type := (others => (others => (others => '0')));
begin
my_print : process is
variable my_line : line;
begin
write(my_line, string'("Value of max_new"));
write(my_line, max_new);
writeline(output, my_line);
wait;
end process my_print;
end architecture test;
我在 运行 模拟时得到的错误是:
错误:'max_new' 附近的类型错误:预期类型 'std_ulogic'。错误:模式 inout 的正式 'l' 必须具有关联的实际值。错误:正式 'value' 没有实际值或默认值。错误:索引名称前缀类型 'void' 不是数组类型
如果我理解正确的话,行类型是一个大小为 3 的数组,在每个位置我都有一个由 4 位组成的向量。 new_type 是一个大小为 2 的数组,在每个位置我都有一个 row_type,这是一个大小为 3 的数组,每个位置都有一个 4 位向量。这个对吗?由于它被初始化为 0,我希望只看到它。
我正在使用 Vivado 2018.3 进行仿真。
非常感谢任何帮助!
std.textio的函数write可以取下列参数作为值(https://www.hdlworks.com/hdl_corner/vhdl_ref/VHDLContents/TEXTIOPackage.htm):
- 位
- bit_vector
- 布尔值
- 字符
- 整数
- 真实
- 字符串
- 时间
IEEE.std_logic_textio 将 std_logic 及其派生项添加到此列表,但 Array 未由 write.
处理
您可以像这样打印数组:
my_print : process is
variable my_line : line;
begin
write(my_line, string'("Value of max_new"));
for I in 0 to 1 loop
for J in 0 to 2 loop
write(my_line, max_new(I)(J));
end loop;
end loop;
writeline(output, my_line);
wait;
end process my_print;
您也可以编写自己的写入程序:
entity hello_world is
end entity hello_world;
-- library STD;
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
-- use IEEE.numeric_std.all;
architecture test of hello_world is
type row_type is array(0 to 2) of std_logic_vector(3 downto 0);
type new_type is array(0 to 1) of row_type;
signal max_new : new_type := (others => (others => (others => '0')));
procedure write (l: inout line; new_type_val: in new_type) is
begin
write (l, string'("("));
for i in new_type'range loop
write (l, string'("("));
for j in row_type'range loop
write (l, string'(""""));
write(l, new_type_val(i)(j));
write (l, string'(""""));
if j /= row_type'right then
write(l, string'(","));
end if;
end loop;
write (l, string'(")"));
if i /= new_type'right then
write(l, string'(","));
end if;
end loop;
write (l, string'(")"));
end procedure;
begin
my_print:
process is
variable my_line: line;
begin
write(my_line, string'("Value of max_new = "));
write(my_line, max_new);
writeline(output, my_line);
wait;
end process my_print;
end architecture test;
ghdl -r hello_world
Value of max_new = (("0000","0000","0000"),("0000","0000","0000"))
使用预先存在的写入过程重载作为构建块。
您还可以使用类型特定的字符串转换来消除对 Synopsys 包的依赖 std_logic_textio 以及引入使用报告语句的能力:
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
architecture no_std_logic_textio of hello_world is
type row_type is array(0 to 2) of std_logic_vector(3 downto 0);
type new_type is array(0 to 1) of row_type;
signal max_new : new_type := (others => (others => (others => '0')));
-- For VHDL version < -2008:
function to_string (inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end function;
function to_string (nt: new_type) return string is
variable l: line;
begin
write (l, string'("("));
for i in new_type'range loop
write (l, string'("("));
for j in row_type'range loop
write (l, '"' & to_string(nt(i)(j)) & '"');
if j /= row_type'right then
write(l, string'(","));
end if;
end loop;
write (l, string'(")"));
if i /= new_type'right then
write(l, string'(","));
end if;
end loop;
write (l, string'(")"));
return l.all;
end function;
begin
my_print:
process is
variable my_line: line;
begin
write (my_line, string'("value of max_new = "));
write(my_line, to_string(max_new));
writeline(output, my_line);
report LF & HT & "max_new = " & to_string(max_new);
wait;
end process my_print;
end architecture no_std_logic_textio;
这演示了写入 output
和报告语句:
ghdl -r hello_world
value of max_new = (("0000","0000","0000"),("0000","0000","0000"))
hello_world.vhdl:95:9:@0ms:(report note):
max_new = (("0000","0000","0000"),("0000","0000","0000"))
我是 VHDL 的新手,我正在 运行 从我得到的代码中摘录一些代码,看看它在做什么。我想在控制台中看到一个自定义数组类型,但是当我尝试编写它时出现错误。
entity hello_world is
end entity hello_world;
library STD;
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
architecture test of hello_world is
type row_type is array(0 to 2) of std_logic_vector(3 downto 0);
type new_type is array(0 to 1) of row_type;
signal max_new : new_type := (others => (others => (others => '0')));
begin
my_print : process is
variable my_line : line;
begin
write(my_line, string'("Value of max_new"));
write(my_line, max_new);
writeline(output, my_line);
wait;
end process my_print;
end architecture test;
我在 运行 模拟时得到的错误是:
错误:'max_new' 附近的类型错误:预期类型 'std_ulogic'。错误:模式 inout 的正式 'l' 必须具有关联的实际值。错误:正式 'value' 没有实际值或默认值。错误:索引名称前缀类型 'void' 不是数组类型
如果我理解正确的话,行类型是一个大小为 3 的数组,在每个位置我都有一个由 4 位组成的向量。 new_type 是一个大小为 2 的数组,在每个位置我都有一个 row_type,这是一个大小为 3 的数组,每个位置都有一个 4 位向量。这个对吗?由于它被初始化为 0,我希望只看到它。
我正在使用 Vivado 2018.3 进行仿真。
非常感谢任何帮助!
std.textio的函数write可以取下列参数作为值(https://www.hdlworks.com/hdl_corner/vhdl_ref/VHDLContents/TEXTIOPackage.htm):
- 位
- bit_vector
- 布尔值
- 字符
- 整数
- 真实
- 字符串
- 时间
IEEE.std_logic_textio 将 std_logic 及其派生项添加到此列表,但 Array 未由 write.
处理您可以像这样打印数组:
my_print : process is
variable my_line : line;
begin
write(my_line, string'("Value of max_new"));
for I in 0 to 1 loop
for J in 0 to 2 loop
write(my_line, max_new(I)(J));
end loop;
end loop;
writeline(output, my_line);
wait;
end process my_print;
您也可以编写自己的写入程序:
entity hello_world is
end entity hello_world;
-- library STD;
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
-- use IEEE.numeric_std.all;
architecture test of hello_world is
type row_type is array(0 to 2) of std_logic_vector(3 downto 0);
type new_type is array(0 to 1) of row_type;
signal max_new : new_type := (others => (others => (others => '0')));
procedure write (l: inout line; new_type_val: in new_type) is
begin
write (l, string'("("));
for i in new_type'range loop
write (l, string'("("));
for j in row_type'range loop
write (l, string'(""""));
write(l, new_type_val(i)(j));
write (l, string'(""""));
if j /= row_type'right then
write(l, string'(","));
end if;
end loop;
write (l, string'(")"));
if i /= new_type'right then
write(l, string'(","));
end if;
end loop;
write (l, string'(")"));
end procedure;
begin
my_print:
process is
variable my_line: line;
begin
write(my_line, string'("Value of max_new = "));
write(my_line, max_new);
writeline(output, my_line);
wait;
end process my_print;
end architecture test;
ghdl -r hello_world
Value of max_new = (("0000","0000","0000"),("0000","0000","0000"))
使用预先存在的写入过程重载作为构建块。
您还可以使用类型特定的字符串转换来消除对 Synopsys 包的依赖 std_logic_textio 以及引入使用报告语句的能力:
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
architecture no_std_logic_textio of hello_world is
type row_type is array(0 to 2) of std_logic_vector(3 downto 0);
type new_type is array(0 to 1) of row_type;
signal max_new : new_type := (others => (others => (others => '0')));
-- For VHDL version < -2008:
function to_string (inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end function;
function to_string (nt: new_type) return string is
variable l: line;
begin
write (l, string'("("));
for i in new_type'range loop
write (l, string'("("));
for j in row_type'range loop
write (l, '"' & to_string(nt(i)(j)) & '"');
if j /= row_type'right then
write(l, string'(","));
end if;
end loop;
write (l, string'(")"));
if i /= new_type'right then
write(l, string'(","));
end if;
end loop;
write (l, string'(")"));
return l.all;
end function;
begin
my_print:
process is
variable my_line: line;
begin
write (my_line, string'("value of max_new = "));
write(my_line, to_string(max_new));
writeline(output, my_line);
report LF & HT & "max_new = " & to_string(max_new);
wait;
end process my_print;
end architecture no_std_logic_textio;
这演示了写入 output
和报告语句:
ghdl -r hello_world
value of max_new = (("0000","0000","0000"),("0000","0000","0000"))
hello_world.vhdl:95:9:@0ms:(report note):
max_new = (("0000","0000","0000"),("0000","0000","0000"))