有没有办法找出我的错误在哪里?
Is there a way I can find out where my error is?
我正在尝试创建 Verilog 代码以在 Hneemann's Digital 上生成秒表,但出现了一些错误。没有迹象表明我的错误在哪里,所以我无法确定在哪里寻找它们。我会 post 下面的代码,看看是否有人能发现它。
module cronometro(
input clk,
input rst,
input [6:0] minuto,
input start,
output [6:0] m1,
output [6:0] m2,
output [6:0] s3,
output [6:0] s4
);
parameter q0 = 3'd0, q1 = 3'd1, q2 = 3'd2, q3 = 3'd3, q4 = 3'd4, q5 = 3'd5;
reg [7:0] a, b, n;
reg [7:0] snA, snB, snN;
reg [2:0] cs, ns;
always @(*)
begin
case(cs)
q0: ns = q1;
q1: ns = a!= n? q2:q6;
q2: ns = q3;
q3: ns = b!=8'd60? q2:q4;
q4:ns = q1;
q5: ns = q5;
default: begin
ns = q0;
end
endcase
always @(posedge clk) begin
if(rst)
cs <= q0;
else
cs <= ns;
end
always @(posedge clk) begin
a <= snA;
b <= snB;
end
always @(*) begin
if (enabled) begin
case(cs)
q0: begin
snA = 8'd0;
snB = 8'd0;
snN = minuto;
end
q1: begin
snA = a;
snB = b;
snN = minuto;
end
q2: begin
snA = a;
snB = b + 8'd1;
snN = minuto;
end
q3: begin
snA = a;
snB = b;
snN = minuto;
end
q4: begin
snA = a + 8'd1;
snB = 8'd0;
snN = minuto;
end
q5: begin
snA = a;
snB = b;
snN = minuto;
end
default: begin
snA = 8'd0;
snB = 8'd0;
snN = minuto;
end
endcase
end
end
end
endmodule
错误是:
jdoodle.v:37: 语法错误
jdoodle.v:39: 赋值语句左值语法。
jdoodle.v:40: 语法错误
jdoodle.v:41: 赋值语句左值语法。
jdoodle.v:100: 语法错误
我放弃了
由于以下原因,我遇到了几个编译错误:
- 不匹配
begin/end
由于缩进不一致。
- 未声明的信号:
enabled
、q6
?
运算符周围缺少空格。
当您不理解错误消息时,请在其他模拟器上尝试您的代码,例如 edaplayground.
上的模拟器
这段代码对我来说编译没有错误:
module cronometro(
input clk,
input rst,
input [6:0] minuto,
input start,
output [6:0] m1,
output [6:0] m2,
output [6:0] s3,
output [6:0] s4
);
parameter q0 = 3'd0, q1 = 3'd1, q2 = 3'd2, q3 = 3'd3, q4 = 3'd4, q5 = 3'd5;
reg [7:0] a, b, n;
reg [7:0] snA, snB, snN;
reg [2:0] cs, ns;
reg enabled, q6;
always @(*)
begin
case(cs)
q0: ns = q1;
q1: ns = a != n ? q2 : q6;
q2: ns = q3;
q3: ns = b != 8'd60 ? q2 : q4;
q4:ns = q1;
q5: ns = q5;
default: begin
ns = q0;
end
endcase
end
always @(posedge clk) begin
if(rst)
cs <= q0;
else
cs <= ns;
end
always @(posedge clk) begin
a <= snA;
b <= snB;
end
always @(*) begin
if (enabled) begin
case(cs)
q0: begin
snA = 8'd0;
snB = 8'd0;
snN = minuto;
end
q1: begin
snA = a;
snB = b;
snN = minuto;
end
q2: begin
snA = a;
snB = b + 8'd1;
snN = minuto;
end
q3: begin
snA = a;
snB = b;
snN = minuto;
end
q4: begin
snA = a + 8'd1;
snB = 8'd0;
snN = minuto;
end
q5: begin
snA = a;
snB = b;
snN = minuto;
end
default: begin
snA = 8'd0;
snB = 8'd0;
snN = minuto;
end
endcase
end
end
endmodule
我正在尝试创建 Verilog 代码以在 Hneemann's Digital 上生成秒表,但出现了一些错误。没有迹象表明我的错误在哪里,所以我无法确定在哪里寻找它们。我会 post 下面的代码,看看是否有人能发现它。
module cronometro(
input clk,
input rst,
input [6:0] minuto,
input start,
output [6:0] m1,
output [6:0] m2,
output [6:0] s3,
output [6:0] s4
);
parameter q0 = 3'd0, q1 = 3'd1, q2 = 3'd2, q3 = 3'd3, q4 = 3'd4, q5 = 3'd5;
reg [7:0] a, b, n;
reg [7:0] snA, snB, snN;
reg [2:0] cs, ns;
always @(*)
begin
case(cs)
q0: ns = q1;
q1: ns = a!= n? q2:q6;
q2: ns = q3;
q3: ns = b!=8'd60? q2:q4;
q4:ns = q1;
q5: ns = q5;
default: begin
ns = q0;
end
endcase
always @(posedge clk) begin
if(rst)
cs <= q0;
else
cs <= ns;
end
always @(posedge clk) begin
a <= snA;
b <= snB;
end
always @(*) begin
if (enabled) begin
case(cs)
q0: begin
snA = 8'd0;
snB = 8'd0;
snN = minuto;
end
q1: begin
snA = a;
snB = b;
snN = minuto;
end
q2: begin
snA = a;
snB = b + 8'd1;
snN = minuto;
end
q3: begin
snA = a;
snB = b;
snN = minuto;
end
q4: begin
snA = a + 8'd1;
snB = 8'd0;
snN = minuto;
end
q5: begin
snA = a;
snB = b;
snN = minuto;
end
default: begin
snA = 8'd0;
snB = 8'd0;
snN = minuto;
end
endcase
end
end
end
endmodule
错误是:
jdoodle.v:37: 语法错误
jdoodle.v:39: 赋值语句左值语法。
jdoodle.v:40: 语法错误
jdoodle.v:41: 赋值语句左值语法。
jdoodle.v:100: 语法错误
我放弃了
由于以下原因,我遇到了几个编译错误:
- 不匹配
begin/end
由于缩进不一致。 - 未声明的信号:
enabled
、q6
?
运算符周围缺少空格。
当您不理解错误消息时,请在其他模拟器上尝试您的代码,例如 edaplayground.
上的模拟器这段代码对我来说编译没有错误:
module cronometro(
input clk,
input rst,
input [6:0] minuto,
input start,
output [6:0] m1,
output [6:0] m2,
output [6:0] s3,
output [6:0] s4
);
parameter q0 = 3'd0, q1 = 3'd1, q2 = 3'd2, q3 = 3'd3, q4 = 3'd4, q5 = 3'd5;
reg [7:0] a, b, n;
reg [7:0] snA, snB, snN;
reg [2:0] cs, ns;
reg enabled, q6;
always @(*)
begin
case(cs)
q0: ns = q1;
q1: ns = a != n ? q2 : q6;
q2: ns = q3;
q3: ns = b != 8'd60 ? q2 : q4;
q4:ns = q1;
q5: ns = q5;
default: begin
ns = q0;
end
endcase
end
always @(posedge clk) begin
if(rst)
cs <= q0;
else
cs <= ns;
end
always @(posedge clk) begin
a <= snA;
b <= snB;
end
always @(*) begin
if (enabled) begin
case(cs)
q0: begin
snA = 8'd0;
snB = 8'd0;
snN = minuto;
end
q1: begin
snA = a;
snB = b;
snN = minuto;
end
q2: begin
snA = a;
snB = b + 8'd1;
snN = minuto;
end
q3: begin
snA = a;
snB = b;
snN = minuto;
end
q4: begin
snA = a + 8'd1;
snB = 8'd0;
snN = minuto;
end
q5: begin
snA = a;
snB = b;
snN = minuto;
end
default: begin
snA = 8'd0;
snB = 8'd0;
snN = minuto;
end
endcase
end
end
endmodule