.sum() 和 .max() 未包含在 Systemverilog 中？

Question

为什么错误说 sum/max“未在此前缀下声明”？我认为 Systemverilog 包含这些数组缩减函数。我需要添加库或其他东西才能使用它们吗？代码如下：

module compare_block (clk, result, data, led);

    parameter taps = 50; //number of fir filter taps
    parameter data_width = 8; //width of data input including sign bit
    parameter coeff_width = 32; //width of coefficients including sign bit
    parameter size = 4096;

    
    input clk;
    input [(data_width + coeff_width + $clog2(taps) - 1):0] result; //from filter
    input [(data_width-1):0] data; //precalculated 1 Hz sine wave
    output led;
    
    reg [(data_width + coeff_width + $clog2(taps) - 1):0] filt_sig;
    reg [(data_width-1):0] comp_sig;
    reg [(data_width-1):0] ans_sig;
    
    integer i;
    integer ii;
    integer sum_array;
    integer array_avg;

        
    always @(posedge clk)
        begin
        filt_sig [(data_width + coeff_width + $clog2(taps) - 1):0]<= result[(data_width + coeff_width + $clog2(taps) - 1):0];
        comp_sig [(data_width-1):0]<= data[(data_width-1):0];
        end
        
    always @(*)
        begin
        for (i=0; i < size; i=i+1)
            ans_sig[i] = filt_sig[i] - comp_sig[i]; 
        end
        assign sum = ans_sig.sum(); //with (int'(item)) 
        assign array_avg = sum >> 'd12; //dividing by 4096 (size) to get mean of signal deviation
        
    integer max_array = ans_sig.max();
    integer error_val = 0.5*max_array;  
    always @(*)
        begin 
        if (array_avg < error_val) begin
            led <= 'b1; 
        end else begin
            led <= 'b0;
        end
    end
endmodule

Answer 1

数组缩减方法是为解包数组定义的。您可以使用 $countones(ans_sig) 而不是 sum()。我不确定您要使用 max() 计算什么。也许您打算将 ans_sig 声明为未打包的数组。

.sum() 和 .max() 未包含在 Systemverilog 中？

.sum() and .max() not included in Systemverilog?

system-verilog