vivado simulation error: Iteration limit 10000 is reached

Question

当我尝试运行在 vivado 中进行模拟时，我得到：

ERROR: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation time can not advance. Please check your source code. Note that the iteration limit can be changed using switch -maxdeltaid. Time: 10 ns Iteration: 10000

我正在测试的模块中没有任何初始语句。

谁能指出问题出在哪里？

`timescale 1ns / 1ps

module mulp(
input clk,
input rst,
input start,
input [4:0] mplier,  // -13
input [4:0] mplcant, // -9
output reg done,
output [9:0] product
);

parameter N = 6;
parameter Idle = 2'b00;
parameter Load = 2'b01;
parameter Oper = 2'b10;
parameter Finish = 2'b11;

reg done_r;
reg [N-1:0] A, A_r, B, B_r;
reg [1:0] state, state_r;
reg [2:0] count, count_r; 

wire [N-2:0] C, C_comp;
reg [N-2:0] C_r;
   
assign C = mplcant; assign C_comp = {~C + 1};
assign product = {A_r[N-2:0], B_r[N-2:0]};

always @(posedge clk) begin
    if (rst) begin
        state_r <= Idle;
        count_r <= 0;
        done_r <= 0;
        A_r <= 0;
        B_r <= 0;
    end else begin
        state_r <= state;
        count_r <= count;
        done_r <= done;
        A_r <= A;
        B_r <= B;
    end // if
end // always

always @(*) begin
    state = state_r;
    count = count_r - 1; // count: 6
    done = done_r;
    A = A_r;
    B = B_r;
    
    case (state) 
        Idle: begin
            if (start) begin
                state <= Load;
            end // if
        end
        Load: begin
            A = 0; B = {mplier, 1'b0}; count = N; // start at 6
            state = Oper;
        end
        Oper: begin
            if (count == 0)
                state = Finish;
            else begin
                case (B[1:0])
                    2'b01: begin
                        // add C to A
                        A = A_r + {C[N-2], C[N-2:0]};
                        // shift A and B
                        A = {A_r[N-1], A_r[N-1:1]};
                        B = {A_r[0], B_r[N-1:1]};
                    end
                    2'b10: begin
                        A = A_r + {C_comp[N-2], C_comp[N-2:0]};
                        A = {A_r[N-1], A[N-1:1]};
                        B = {A_r[0], B_r[N-1:1]};
                    end
                    (2'b00 | 2'b11): begin
                        A = {A_r[N-1], A[N-1:1]};
                        B = {A_r[0], B_r[N-1:1]}; 
                    end
                    default: begin
                        state = Idle; done = 1'bx; // error
                    end
                endcase  
            end // else
        end // Oper
        Finish: begin
            done = 1; 
            state = Idle;
        end // Finish
        default: begin
            done = 1'bx;
            state = Idle;
        end 
    endcase
end // always

endmodule

Answer 1

你有一个组合循环。您正在对 always 组合块中的 state 信号进行采样和驱动。通常，您在 FSM 中对注册的状态变量（代码中的 state_r）进行采样。变化：

case (state)

至：

case (state_r)

不相关，但您应该在组合块中使用所有阻塞赋值（不是混合）。变化：

            state <= Load;

至：

            state = Load;

vivado simulation error: Iteration limit 10000 is reached

vivado simulation error: Iteration limit 10000 is reached

simulation

verilog