超线程数据缓存上下文别名
Hyper-Threading data cache context aliasing
在 intel 的手册中，以下部分让我感到困惑：
11.5.6.2 Shared Mode In shared mode, the L1 data cache is competitively shared between logical processors. This is true even if
the logical processors use identical CR3 registers and paging modes.
In shared mode, linear addresses in the L1 data cache can be aliased,
meaning that one linear address in the cache can point to different
physical locations. The mechanism for resolving aliasing can lead to
thrashing. For this reason, IA32_MISC_ENABLE[bit 24] = 0 is the
preferred configuration for processors based on the Intel NetBurst
microarchitecture that support Intel Hyper-Threading Technology.
因为英特尔使用 VIPT（等于 PIPT）访问缓存。
缓存别名是如何发生的？
基于 英特尔® 64 位和 IA-32 架构优化参考手册，2009 年 11 月 (248966-020)，第 2.6.1.3 节：
Most resources in a physical processor are fully shared to improve the
dynamic utilization of the resource, including caches and all the
execution units. Some shared resources which are linearly addressed,
like the DTLB, include a logical processor ID bit to distinguish
whether the entry belongs to one logical processor or the other.
The first level cache can operate in two modes depending on a context-ID
bit:
- Shared mode: The L1 data cache is fully shared by two logical
processors.
- Adaptive mode: In adaptive mode, memory accesses using the page
directory is mapped identically across logical processors sharing the
L1 data cache.
可能存在别名，因为处理器 ID/context-ID 位（它只是指示内存访问来自哪个虚拟处理器的位）对于不同的线程是不同的，共享模式使用该位。自适应模式只是像人们通常期望的那样简单地寻址缓存，只使用内存地址。
在共享模式下索引缓存时，具体如何使用处理器 ID 似乎没有记录。 （与多个地址位进行异或运算将提供索引的分散，这样一个硬件线程的相邻索引将映射到另一个线程的更多分离索引。为不同线程选择不同的位顺序的可能性较小，因为这往往会增加延迟。分散在给定空间局部性高于缓存行粒度但小于 way-size 粒度的情况下减少冲突频率。）
在 intel 的手册中，以下部分让我感到困惑：
11.5.6.2 Shared Mode In shared mode, the L1 data cache is competitively shared between logical processors. This is true even if the logical processors use identical CR3 registers and paging modes. In shared mode, linear addresses in the L1 data cache can be aliased, meaning that one linear address in the cache can point to different physical locations. The mechanism for resolving aliasing can lead to thrashing. For this reason, IA32_MISC_ENABLE[bit 24] = 0 is the preferred configuration for processors based on the Intel NetBurst microarchitecture that support Intel Hyper-Threading Technology.
因为英特尔使用 VIPT（等于 PIPT）访问缓存。
缓存别名是如何发生的？
基于 英特尔® 64 位和 IA-32 架构优化参考手册，2009 年 11 月 (248966-020)，第 2.6.1.3 节：
Most resources in a physical processor are fully shared to improve the dynamic utilization of the resource, including caches and all the execution units. Some shared resources which are linearly addressed, like the DTLB, include a logical processor ID bit to distinguish whether the entry belongs to one logical processor or the other.
The first level cache can operate in two modes depending on a context-ID bit:
- Shared mode: The L1 data cache is fully shared by two logical processors.
- Adaptive mode: In adaptive mode, memory accesses using the page directory is mapped identically across logical processors sharing the L1 data cache.
可能存在别名，因为处理器 ID/context-ID 位（它只是指示内存访问来自哪个虚拟处理器的位）对于不同的线程是不同的，共享模式使用该位。自适应模式只是像人们通常期望的那样简单地寻址缓存，只使用内存地址。
在共享模式下索引缓存时，具体如何使用处理器 ID 似乎没有记录。 （与多个地址位进行异或运算将提供索引的分散，这样一个硬件线程的相邻索引将映射到另一个线程的更多分离索引。为不同线程选择不同的位顺序的可能性较小，因为这往往会增加延迟。分散在给定空间局部性高于缓存行粒度但小于 way-size 粒度的情况下减少冲突频率。）