带先行进位的 4 位加法器的 Verilog 测试平台

Question

老实说，考虑到我只创建过一次幼稚的简单项目，我对 Verilog 尤其是测试台还是有点不熟悉。我不确定如何为我制作的 Verilog 文件制作测试台，所以我无法测试它是否有效。这是我的代码：

`timescale 1ns/1ps

module adder_4bit_cla(sum, Cout, A, B, S);

    input [3:0] A, B;
    input S;
    output [3:0] sum;
    output Cout;
    
    wire P0, G0, P1, G1, P3, G3;
    wire C4, C3, C2, C1;
    
    assign
        P0 = A[0] ^ B[0],
        P1 = A[1] ^ B[1],
        P2 = A[2] ^ B[2],
        P3 = A[3] ^ B[3];
        
    assign
        G0 = A[0] & B[0],
        G1 = A[1] & B[1],
        G2 = A[2] & B[2],
        G3 = A[3] & B[3];
        
    assign
        C1 = G0 | (P0 & S),
        C2 = G1 | (P1 & G0) | (P1 & P0 & S),
        C3 = G2 | (P2 & G1) | (P2 & P1 & G0) | (P2 & P1 & P0 & S),
        C4 = G3 | (P3 & G2) | (P3 & P2 & G1) | (P3 & P2 & P1 & G0) | (P3 & P2 & P1 & P0 & S);
        
    assign
        sum[0] = P0 ^ S,
        sum[1] = P1 ^ C1,
        sum[2] = P2 ^ C2,
        sum[3] = P3 ^ C3;
        
    assign Cout = C4;
    
endmodule

老实说，我真正需要做的是一个使用先行进位的 4 位加减法器，但我不知道如何开始先行进位，所以我来了。如果有人能帮助我，那就太好了：<

编辑：我已经冷静下来，我终于可以查明确切的问题：测试台的 A 和 B 的值。虽然我可以暴力破解它，但我怎样才能利用循环来增加 A 和 B 以便它像这样：

同时更新 M?

Answer 1

使用以下方法改进您的测试平台。

`timescale 1ns / 1ps

module adder_4bit_cla_tb();

// inputs - keep them having reg as the data type 
reg [3:0] A, B;
reg S;

// outputs - keep them having wire as the data type 
wire [3:0] sum;
wire Cout;


adder_4bit_cla adder_4bit_cla_inst
                  (
                 .sum(sum), .Cout(Cout), .A(A), .B(B), .S(S)
                  );

initial begin
       
    A = 4'd1; B = 4'd2; S = 1'd1;
    
    #10 A = 4'd2; B = 4'd5; S = 1'd0;
    
    #10 A = 4'd5; B = 4'd6; S = 1'd0;

    #50 $stop;
    
end
endmodule

波形结果

可以使用 for 循环提供输入，如下所示。


`timescale 1ns / 1ps

module adder_4bit_cla_tb();

// inputs - keep them having reg as the data type 
reg [3:0] A, B;
reg S;

// outputs - keep them having wire as the data type 
wire [3:0] sum;
wire Cout;

reg [3:0] i; 

adder_4bit_cla adder_4bit_cla_inst
                  (
                 .sum(sum), .Cout(Cout), .A(A), .B(B), .S(S)
                  );

initial begin
     
    for(i = 4'd0; i < 4'd15; i = i + 4'd1) begin  
    
    A = i; B = i; S = 1'b0;
    
    #10;
    
    end
    
    #200 $stop;
    
end
endmodule

波形结果

带先行进位的 4 位加法器的 Verilog 测试平台

Verilog test bench for 4-bit adder with Carry Lookahead

verilog

hdl