我需要将此 VHDL 代码转换为 MyVHDL Python,如何操作?
I need to convert this VHDL code to MyVHDL Python, how to?
我需要在 python 中将此代码转换为 myhdl 以用于我的学校作业,有人可以帮助我吗?
library ieee;
use ieee.std_logic_1164.all;
entity simple_example is
port (
a : in std_logic;
b : in std_logic;
o : out std_logic
);
end simple_example;
architecture simple_example of simple_example is
signal s : std_logic;
begin
s <= a and b;
o <= s or b;
end simple_example;
您可以参考文档:http://docs.myhdl.org/en/stable/manual/preface.html#
您可能会发现以下内容有帮助:
from myhdl import *
@block
def simple_example(a , b, o):
"""
input: a, b
output: o
"""
@always_comb
def behave():
s = a and b
o = s or b
return instances()
"""
Verification
"""
x = Signal(bool(0))
y = Signal(bool(0))
z = Signal(bool(0))
test = simple_example(x, y, z)
test.convert(hdl="VHDL", initial_values=True)
我需要在 python 中将此代码转换为 myhdl 以用于我的学校作业,有人可以帮助我吗?
library ieee;
use ieee.std_logic_1164.all;
entity simple_example is
port (
a : in std_logic;
b : in std_logic;
o : out std_logic
);
end simple_example;
architecture simple_example of simple_example is
signal s : std_logic;
begin
s <= a and b;
o <= s or b;
end simple_example;
您可以参考文档:http://docs.myhdl.org/en/stable/manual/preface.html#
您可能会发现以下内容有帮助:
from myhdl import *
@block
def simple_example(a , b, o):
"""
input: a, b
output: o
"""
@always_comb
def behave():
s = a and b
o = s or b
return instances()
"""
Verification
"""
x = Signal(bool(0))
y = Signal(bool(0))
z = Signal(bool(0))
test = simple_example(x, y, z)
test.convert(hdl="VHDL", initial_values=True)