What is wrong with my code near "generate fulladder" (Error: module is not defined)?

Question

我正在用 SystemVerilog 编写程序，并且正在尝试制作一个 n 位超前加法器。我对 generate 有疑问；我收到以下错误：

** Error: design.sv(13): Module 'fulladder' is not defined.
#  For instance 'f0' at path 'carry_lookahead_adder_tb.carry_lookahead_inst'
# ** Error: design.sv(17): Module 'fulladder' is not defined.
#  For instance 'fi' at path 'carry_lookahead_adder_tb.carry_lookahead_inst.f_loop'
# ** Error: design.sv(17): Module 'fulladder' is not defined.
#  For instance 'fi' at path 'carry_lookahead_adder_tb.carry_lookahead_inst.f_loop'
# Optimization failed

第 13 行是 fulladder f0...


module carry_lookahead_adder
  #(parameter WIDTH=32)
  (input logic [WIDTH-1:0] i_add1,
   input logic [WIDTH-1:0] i_add2,
   output logic [WIDTH:0] o_result
  );
  logic [WIDTH:0]  w_C;
  logic [WIDTH-1:0] w_G, w_P, w_SUM;
  
  //Generate full adders
  genvar i;
  fulladder f0 (i_bit1(i_add1[0]), i_bit2(i_add2[0]),i_carry(w_C[0]), o_sum(w_SUM[0]), o_carry());
  generate for (i= 1; i<WIDTH; i++)
    begin : f_loop   
      
      fulladder fi
      (i_bit1(i_add1[i]),
        i_bit2(i_add2[i]),
        i_carry(w_C[i]),
        o_sum(w_SUM[i]),
        o_carry()
      );
    end 
  endgenerate
  
  genvar jj;
  generate 
    for (jj=0; jj<WIDTH; jj++)
      begin
        assign w_G[jj]  = i_add1[jj] & i_add2[jj];
        assign w_P[jj]  = i_add1[jj] | i_add2[jj];
        assign w_C[jj+1] = w_G[jj] | (w_P[jj] & w_C[jj]);
      end
  endgenerate     
    
      assign w_C[0] = 1'b0; //No carry input
     
  assign o_result = {w_C[WIDTH], w_SUM};
                                          
endmodule

我知道我 creating/calling 功能有误，但我找不到任何关于如何正确执行的好资源。

Answer 1

这些错误与 generate 构造无关。这些错误只是告诉您 fulladder 模块未定义。这意味着您在编译 Verilog 代码时没有包含该模块。

请注意，第一条错误消息指的是不在 generate 内的实例 f0。当我运行你在 edaplayground 上的代码删除了所有 generate 代码时，我收到相同的错误消息：

module carry_lookahead_adder
  #(parameter WIDTH=32)
  (input logic [WIDTH-1:0] i_add1,
   input logic [WIDTH-1:0] i_add2,
   output logic [WIDTH:0] o_result
  );
  logic [WIDTH:0]  w_C;
  logic [WIDTH-1:0] w_G, w_P, w_SUM;
  
  //Generate full adders
  genvar i;
  fulladder f0 (i_bit1(i_add1[0]), i_bit2(i_add2[0]),i_carry(w_C[0]), o_sum(w_SUM[0]), o_carry());
endmodule

# ** Error: testbench.sv(13): Module 'fulladder' is not defined.
#  For instance 'f0' at path 'carry_lookahead_adder'

design.sv 文件似乎没有 fulladder 模块。您需要将模块添加到该文件，或者（更有可能）指示您的模拟器使用其中的 fulladder 模块编译文件。

您的模块实例化中也存在语法错误。按名称使用连接时，需要在端口名称前使用句点。比如需要使用.i_bit1(i_add1[0])等：

fulladder f0 (.i_bit1(i_add1[0]), .i_bit2(i_add2[0]),.i_carry(w_C[0]), .o_sum(w_SUM[0]), .o_carry());

What is wrong with my code near "generate fulladder" (Error: module is not defined)?

What is wrong with my code near "generate fulladder" (Error: module is not defined)?

verilog

system-verilog