verilog if-else 错误消息

Question

我对 verilog if-else 语句有疑问。我正在尝试制作一个数字时钟和我的 tick_counter 模块代码，如下所示。我用注释行指向错误行。我找不到解决方法，请帮助我。

module tick_counter(
input clk,
input tick_in,
output [3:0] ssd_2, ssd_4,
output [2:0] ssd_3
);
reg [5:0] count1, count_next1;
reg [2:0] count2, count_next2;
reg [3:0] count3, count4, count_next3, count_next4;

always@(posedge clk)
    begin
        count1 <= count_next1;
        count2 <= count_next2;
        count3 <= count_next3;
        count4 <= count_next4;
    end
//next state logic
always@*
    begin
        if(tick_in)
            begin
                if(count1==6'b111100)               //second counter
                    begin
                        count_next1 = 6'b0;
                        count_next2 = count2 + 1'b1;
                    end
                else
                    count_next1 = count1 + 1'b1;
                if(count2==4'b1001)                 //minutes counter of LSB digit
                    begin
                        count_next2 = 4'b0000;
                        count_next3 = count3 + 1'b1;
                    end
                else
                    count_next2 = count2 + 1'b1;
                if(count3==3'b101)                  //minutes counter of MSB digit
                    begin
                        count_next3 = 3'b000;
                        count_next4 = count4 + 1'b1;
                    end
                else
                    count_next3 = count3 + 1'b1;
                if(count4==4'b1001)                 //counter hour
                    begin                 
                        count_next4 = 4'b0000;
                    end
                else
                    count_next4 = count4 + 1'b1;
        else                                        //---THE POINT OF ERROR------
            begin
                count_next1 = count1;
                count_next2 = count2;
                count_next3 = count3;
                count_next4 = count4;
            end
    end
end


    assign ssd_2 = count2;
    assign ssd_3 = count3;
    assign ssd_4 = count4;

endmodule

Answer 1

当然少了endmodule。但这可能是你的错字。

对于大型设计，强烈建议使用适当的缩进。在这里，在缩进您的代码后，我了解到 end 在 // counter hour 条件的 else 部分之后丢失了。因此，您的主要 if 条件 end 放错了位置。只需在指定位置添加 end 并从最后一个 always 块中删除一个 end.

请适当缩进，以便调试。

verilog if-else 错误消息

verilog if-else error message

if-statement

verilog